Welcome![Sign In][Sign Up]
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: verilog_rs232 Download
 Description: verilog UART controller
 Downloaders recently: [More information of uploader bigchop]
 To Search: verilog rs2
  • [can] - the implention of can bus with verilog
File list (Check if you may need any files):
s6_rs232\project\bitgen.ut
........\.......\core.tpl
........\.......\div.cmd_log
........\.......\div.lso
........\.......\div.ngc
........\.......\div.ngr
........\.......\div.prj
........\.......\div.spl
........\.......\div.stx
........\.......\div.sym
........\.......\div.syr
........\.......\div.v
........\.......\div_summary.html
........\.......\div_vhdl.prj
........\.......\filter.spl
........\.......\filter.sym
........\.......\filter.v
........\.......\project.dhp
........\.......\project.ise
........\.......\project.ise_ISE_Backup
........\.......\rcvr.v
........\.......\top.bgn
........\.......\top.bit
........\.......\top.bld
........\.......\top.cel
........\.......\top.cmd_log
........\.......\top.drc
........\.......\top.lfp
........\.......\top.lso
........\.......\top.mrp
........\.......\top.nc1
........\.......\top.ncd
........\.......\top.ngc
........\.......\top.ngd
........\.......\top.ngm
........\.......\top.ngr
........\.......\top.pad
........\.......\top.pad_txt
........\.......\top.par
........\.......\top.pcf
........\.......\top.placed_ncd_tracker
........\.......\top.prj
........\.......\top.routed_ncd_tracker
........\.......\top.sch
........\.......\top.stx
........\.......\top.syr
........\.......\top.twr
........\.......\top.twx
........\.......\top.ucf
........\.......\top.ucf.untf
........\.......\top.ut
........\.......\top.v
........\.......\top.vf
........\.......\top.xpi
........\.......\top_last_par.ncd
........\.......\top_map.ncd
........\.......\top_map.ngm
........\.......\top_pad.csv
........\.......\top_pad.txt
........\.......\top_summary.html
........\.......\top_vhdl.prj
........\.......\txmit.v
........\.......\uart.v
........\.......\uart_if.spl
........\.......\uart_if.sym
........\.......\uart_if.v
........\.......\uart_rom.asy
........\.......\uart_rom.coe
........\.......\uart_rom.edn
........\.......\uart_rom.mif
........\.......\uart_rom.ngo
........\.......\uart_rom.sym
........\.......\uart_rom.v
........\.......\uart_rom.veo
........\.......\uart_rom.vhd
........\.......\uart_rom.vho
........\.......\uart_rom.xco
........\.......\uart_rom_flist.txt
........\.......\uart_rom_readme.txt
........\.......\xst\work\hdllib.ref
........\.......\...\....\vlg15\rcvr.bin
........\.......\...\....\...47\div.bin
........\.......\...\....\....8\uart.bin
........\.......\...\....\...62\uart__if.bin
........\.......\...\....\....5\uart__rom.bin
........\.......\...\....\....F\top.bin
........\.......\...\....\...72\filter.bin
........\.......\...\....\.....\txmit.bin
........\.......\_impact.cmd
........\.......\.ngo\netlist.lst
........\.......\....\uart_rom.ngo
........\.......\_pace.ucf
........\.......\._projnav\bitgen.rsp
........\.......\.........\div.xst
........\.......\.........\ednTOngd_tcl.rsp
........\.......\.........\nc1TOncd_tcl.rsp
........\.......\.........\parentAssignPackagePinsApp_tcl.rsp
........\.......\.........\parentCreateTimingConstraintsApp_tcl.rsp
........\.......\.........\project.gfl
........\.......\.........\project_flowplus.gfl
    

CodeBus www.codebus.net