Description: Standard Verilog HDL language of the IIC bus IP core, a detailed definition of the timing and the input and output, can be applied directly
- [I2CIP] - IIC IP. This is the result of verificati
- [i2c] - This is an IIC interface procedures for
- [FPGA-IIC] - In the FPGA, the realization of IIC data
- [Verilog-IIC] - IIC VerilogHDL languages to read and wri
- [IIC_core] - The above is IIC_CORE module used to imp
- [iic] - My experiment is AT24C08 single-byte rea
File list (Check if you may need any files):
IIC.doc
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