Description: ATMEL Corporation QUETUSii using software written in verilog language program, the realization of a zone reset, adjust the time function of the electronic clock to digital display of time, adjusting time to adjust bit flash
- [flash] - The source code for the FPGA-based FLASH
- [MX29LV160DTB] - 29LV160 or 8/16 anti-FLASH 16Mbit the tr
File list (Check if you may need any files):
eda\apachelicense.txt
...\buddy_license.txt
...\bwidget.txt
...\cmp_state.ini
...\contral.bsf
...\contral.done
...\contral.flow.rpt
...\contral.inc
...\contral.map.rpt
...\contral.qpf
...\contral.qsf
...\contral.qws
...\contral.v
...\count12.asm.rpt
...\count12.done
...\count12.fit.eqn
...\count12.fit.rpt
...\count12.flow.rpt
...\count12.map.eqn
...\count12.map.rpt
...\count12.pin
...\count12.qpf
...\count12.qsf
...\count12.qws
...\count12.sim.rpt
...\count12.tan.rpt
...\count12.tan.summary
...\count12.v
...\count12.vwf
...\db\contral.contral.sld_design_entry.sci
...\..\contral.csf.qmsg
...\..\contral.db_info
...\..\contral.map.qmsg
...\..\contral.project.hdb
...\..\count12-sim.vwf
...\..\count12.asm.qmsg
...\..\count12.cmp.rdb
...\..\count12.count12.sld_design_entry.sci
...\..\count12.csf.qmsg
...\..\count12.db_info
...\..\count12.fit.qmsg
...\..\count12.hif
...\..\count12.icc
...\..\count12.map.hdb
...\..\count12.map.qmsg
...\..\count12.pre_map.hdb
...\..\count12.project.hdb
...\..\count12.rtlv.hdb
...\..\count12.rtlv_sg.cdb
...\..\count12.rtlv_sg_swap.cdb
...\..\count12.sgdiff.cdb
...\..\count12.sgdiff.hdb
...\..\count12.sim.hdb
...\..\count12.sim.qmsg
...\..\count12.sim.rdb
...\..\count12.tan.qmsg
...\..\count12_cmp.qrpt
...\..\count12_hier_info
...\..\count12_sim.qrpt
...\..\count12_syn_hier_info
...\..\decode4-7.db_info
...\..\decode4-7.project.hdb
...\..\fenxian84.asm.qmsg
...\..\fenxian84.cmp.rdb
...\..\fenxian84.csf.qmsg
...\..\fenxian84.db_info
...\..\fenxian84.fenxian84.sld_design_entry.sci
...\..\fenxian84.fit.qmsg
...\..\fenxian84.hif
...\..\fenxian84.icc
...\..\fenxian84.map.hdb
...\..\fenxian84.map.qmsg
...\..\fenxian84.pre_map.hdb
...\..\fenxian84.project.hdb
...\..\fenxian84.rtlv.hdb
...\..\fenxian84.rtlv_sg.cdb
...\..\fenxian84.rtlv_sg_swap.cdb
...\..\fenxian84.sgdiff.cdb
...\..\fenxian84.sgdiff.hdb
...\..\fenxian84.tan.qmsg
...\..\fenxian84_cmp.qrpt
...\..\fenxian84_hier_info
...\..\fenxian84_syn_hier_info
...\..\gate.asm.qmsg
...\..\gate.cmp.rdb
...\..\gate.csf.qmsg
...\..\gate.db_info
...\..\gate.fit.qmsg
...\..\gate.gate.sld_design_entry.sci
...\..\gate.hif
...\..\gate.icc
...\..\gate.map.hdb
...\..\gate.map.qmsg
...\..\gate.pre_map.hdb
...\..\gate.project.hdb
...\..\gate.rtlv.hdb
...\..\gate.rtlv_sg.cdb
...\..\gate.rtlv_sg_swap.cdb
...\..\gate.sgdiff.cdb
...\..\gate.sgdiff.hdb
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