Description: The system top-level module, called 7, the bottom module. Bottom-7 module module: the ideal source of data receiver module, an ideal source of data cache module, LAPS framing module, scrambling and send LAPS frame module, receiving and descrambling module LAPS frame, receive LAPS frame data buffer module, solution frame and sending data to a good source module. The other, there is a fifo module to call the two cache modules.
To Search:
- [LAPS] - Their implementation with a simple LAPS
- [project2_verilog] - Simplify the LAPS protocol, verilog grea
- [sdh1] - This section of code is on the operation
- [PipelinedCPU] - Using Verilog design language of the lin
File list (Check if you may need any files):
vhdl\data_receive.vhd
....\deframe.vhd
....\enframe.vhd
....\fifo.vhd
....\main.vhd
....\readme.txt
....\rxfifo.vhd
....\scram_dncode.vhd
....\scram_encode.vhd
....\txfifo.vhd
vhdl
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