Description: This source code is based on the Verilog language, multiple ways to achieve the 4 S 1 MUX, a variety of ways to achieve the 4 S 2 MUX, a variety of ways to achieve a half adder, a variety of ways to achieve a full adder, ways to achieve the 4-bit full adder, the output of a variety of ways to achieve UDP component, two clock signals, the selector and a variety of simulation source code.
To Search:
- [add] - 4bits
- [FullAdder] - This is a code programed in Verilog Lang
- [adder4] - The Verilog language source code is base
File list (Check if you may need any files):
ADD6.txt
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