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Title: CPU Download
 Description: Cpu functions to achieve simple
 Downloaders recently: [More information of uploader lcy320stud]
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  • [cpu] - fpga to achieve a simple cpu, there are
File list (Check if you may need any files):
CPU\CPU\ALU.v
...\...\CPU.ise
...\...\CPU.ise_ISE_Backup
...\...\CPU.ntrc_log
...\...\CPU.restore
...\...\cpu_rom.asy
...\...\cpu_rom.mif
...\...\cpu_rom.ngc
...\...\cpu_rom.sym
...\...\cpu_rom.v
...\...\cpu_rom.veo
...\...\cpu_rom.vhd
...\...\cpu_rom.vho
...\...\cpu_rom.xco
...\...\cpu_rom_flist.txt
...\...\cpu_rom_readme.txt
...\...\cpu_rom_xmdf.tcl
...\...\cu.v
...\...\GR.v
...\...\KD_CPU.bld
...\...\KD_CPU.cmd_log
...\...\KD_CPU.lso
...\...\KD_CPU.ngc
...\...\KD_CPU.ngd
...\...\KD_CPU.ngr
...\...\KD_CPU.prj
...\...\KD_CPU.spl
...\...\KD_CPU.stx
...\...\KD_CPU.sym
...\...\KD_CPU.syr
...\...\KD_CPU.v
...\...\KD_CPU.xst
...\...\KD_CPU_prev_built.ngd
...\...\mem.v
...\...\mux-2.v
...\...\mux4.v
...\...\pc.v
...\...\register.v
...\...\rom_demo.coe
...\...\templates\coregen.xml
...\...\testbench.fdo
...\...\testbench.udo
...\...\TESTBENCH.v
...\...\tmp\_cg\cpu_rom.mif
...\...\transcript
...\...\vsim.wlf
...\...\work\@a@l@u\verilog.asm
...\...\....\......\_primary.dat
...\...\....\......\_primary.vhd
...\...\....\.c@u\verilog.asm
...\...\....\....\_primary.dat
...\...\....\....\_primary.vhd
...\...\....\.g@r\verilog.asm
...\...\....\....\_primary.dat
...\...\....\....\_primary.vhd
...\...\....\.k@d_@c@p@u\verilog.asm
...\...\....\...........\_primary.dat
...\...\....\...........\_primary.vhd
...\...\....\.p@c\verilog.asm
...\...\....\....\_primary.dat
...\...\....\....\_primary.vhd
...\...\....\cpu_rom\verilog.asm
...\...\....\.......\_primary.dat
...\...\....\.......\_primary.vhd
...\...\....\glbl\verilog.asm
...\...\....\....\_primary.dat
...\...\....\....\_primary.vhd
...\...\....\memory\verilog.asm
...\...\....\......\_primary.dat
...\...\....\......\_primary.vhd
...\...\....\.ux4\verilog.asm
...\...\....\....\_primary.dat
...\...\....\....\_primary.vhd
...\...\....\register\verilog.asm
...\...\....\........\_primary.dat
...\...\....\........\_primary.vhd
...\...\....\testbench\verilog.asm
...\...\....\.........\_primary.dat
...\...\....\.........\_primary.vhd
...\...\....\_info
...\...\xst\dump.xst\KD_CPU.prj\ntrc.scr
...\...\...\work\hdllib.ref
...\...\...\....\vlg24\_c_u.bin
...\...\...\....\....9\register.bin
...\...\...\....\....A\_a_l_u.bin
...\...\...\....\...32\mux4.bin
...\...\...\....\....5\_g_r.bin
...\...\...\....\...53\_p_c.bin
...\...\...\....\....E\_k_d___c_p_u.bin
...\...\...\....\...6D\cpu__rom.bin
...\...\_ngo\netlist.lst
...\...\.xmsgs\ngdbuild.xmsgs
...\...\......\xst.xmsgs
...\...\xst\dump.xst\KD_CPU.prj\ngx\notopt
...\...\...\........\..........\...\opt
...\...\...\........\..........\ngx
...\...\...\........\KD_CPU.prj
...\...\...\work\vlg24
...\...\...\....\vlg29
...\...\...\....\vlg2A
    

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