Welcome![Sign In][Sign Up]
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: LogicLock Download
 Description: Digital mixer, verilog and mixed programming schematic
 Downloaders recently: [More information of uploader zpe.cn]
 To Search:
  • [CORDIC_mixer] - FPGA can be achieved, the use of the NCO
  • [LogicLock] - ALTERA FPGACPLD High chapter LogicLock
  • [ddc] - Digital Down Converter for matlab realiz
  • [DDCFPGA] - For the DVB-T standard ETSI EN 300 744 V
  • [LogicLock] - logiclock functional demo vhdl language
  • [DDC_prj1] - this is a project about digital down-con
  • [FPGAspwm] - In Xilinx' s Spartan Ⅱ E Series XC2S1
  • [DDSSYNCtrl_tri_face] - AD9910 experimental code, the use of par
File list (Check if you may need any files):
LogicLock\ADfifo.bsf
.........\ADfifo.qip
.........\ADfifo.v
.........\ADfifo_bb.v
.........\ADfifo_wave0.jpg
.........\ADfifo_wave1.jpg
.........\ADfifo_waveforms.html
.........\atom_netlists\LogicLock.vqm
.........\BAUD_GENERATER.v
.........\BAUD_GENERATER.v.bak
.........\control_test.bsf
.........\CosRom.bsf
.........\CosRom.qip
.........\CosRom.v
.........\CosRom_bb.v
.........\CosRom_wave0.jpg
.........\CosRom_waveforms.html
.........\db\altsyncram_1cq3.tdf
.........\..\altsyncram_4rs3.tdf
.........\..\altsyncram_76p3.tdf
.........\..\altsyncram_aos3.tdf
.........\..\altsyncram_cos3.tdf
.........\..\altsyncram_d3p3.tdf
.........\..\altsyncram_k971.tdf
.........\..\altsyncram_n0p3.tdf
.........\..\altsyncram_p971.tdf
.........\..\cmpr_7dc.tdf
.........\..\cmpr_adc.tdf
.........\..\cmpr_bdc.tdf
.........\..\cmpr_cdc.tdf
.........\..\cmpr_ddc.tdf
.........\..\cntr_06j.tdf
.........\..\cntr_23j.tdf
.........\..\cntr_6di.tdf
.........\..\cntr_8di.tdf
.........\..\cntr_ivi.tdf
.........\..\cntr_kei.tdf
.........\..\cntr_uci.tdf
.........\..\cntr_vci.tdf
.........\..\decode_6pa.tdf
.........\..\decode_trf.tdf
.........\..\LogicLock.ace_cmp.bpm
.........\..\LogicLock.ace_cmp.cdb
.........\..\LogicLock.ace_cmp.ecobp
.........\..\LogicLock.ace_cmp.hdb
.........\..\LogicLock.analyze_file.qmsg
.........\..\LogicLock.asm.qmsg
.........\..\LogicLock.asm.rdb
.........\..\LogicLock.asm_labs.ddb
.........\..\LogicLock.cbx.xml
.........\..\LogicLock.cdb.qmsg
.........\..\LogicLock.cmp.bpm
.........\..\LogicLock.cmp.cdb
.........\..\LogicLock.cmp.ecobp
.........\..\LogicLock.cmp.hdb
.........\..\LogicLock.cmp.kpt
.........\..\LogicLock.cmp.logdb
.........\..\LogicLock.cmp.rdb
.........\..\LogicLock.cmp.tdb
.........\..\LogicLock.cmp0.ddb
.........\..\LogicLock.cmp2.ddb
.........\..\LogicLock.cmp_merge.kpt
.........\..\LogicLock.db_info
.........\..\LogicLock.eco.cdb
.........\..\LogicLock.fit.qmsg
.........\..\LogicLock.hier_info
.........\..\LogicLock.hif
.........\..\LogicLock.lpc.html
.........\..\LogicLock.lpc.rdb
.........\..\LogicLock.lpc.txt
.........\..\LogicLock.map.bpm
.........\..\LogicLock.map.cdb
.........\..\LogicLock.map.ecobp
.........\..\LogicLock.map.hdb
.........\..\LogicLock.map.kpt
.........\..\LogicLock.map.logdb
.........\..\LogicLock.map.qmsg
.........\..\LogicLock.map_bb.cdb
.........\..\LogicLock.map_bb.hdb
.........\..\LogicLock.map_bb.logdb
.........\..\LogicLock.merge.qmsg
.........\..\LogicLock.pre_map.cdb
.........\..\LogicLock.pre_map.hdb
.........\..\LogicLock.rtlv.hdb
.........\..\LogicLock.rtlv_sg.cdb
.........\..\LogicLock.rtlv_sg_swap.cdb
.........\..\LogicLock.sgdiff.cdb
.........\..\LogicLock.sgdiff.hdb
.........\..\LogicLock.sld_design_entry.sci
.........\..\LogicLock.sld_design_entry_dsc.sci
.........\..\LogicLock.smart_action.txt
.........\..\LogicLock.syn_hier_info
.........\..\LogicLock.tan.qmsg
.........\..\LogicLock.tis_db_list.ddb
.........\..\LogicLock.tmw_info
.........\..\LogicLock_global_asgn_op.abo
.........\..\logic_util_heursitic.dat
.........\..\lpm_constant_1d8.tdf
.........\..\lpm_constant_8d8.tdf
.........\..\lpm_constant_dd8.tdf
    

CodeBus www.codebus.net