pipelined_fft_64 Written using Verilog IP Core pro

Title: pipelined_fft_64

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Category:
VHDL-FPGA-Verilog
Tags:
[ASM] [源码]
File Size:
97kb
Update:
2012-11-26
Downloads:
0 Times
Uploaded by:
chengyungang123

Description: Written using Verilog IP Core procedures to achieve FFT transformation, we want to help.

Downloaders recently: [More information of uploader chengyungang123]

To Search: fft verilog verilog fft

[fft_verilog] - FFT IP core
[fft_gen] - FFT vhdl generic: I m new to vhdl, and I
[5f4513d8-522d-4f8f-96b8-41136b2c8972] - fft implementation RTL code, just only a
[64R4SDFpoint_FFT] - The project implements a 64-point FFT, v
[TS201] - ADSP-TS201 introduced some of the parame

File list (Check if you may need any files):

pipelined_fft_64\trunk\BENCH\sinerom64_gen.pl
................\.....\.....\sin_tst_rom.v
................\.....\.....\USFFT64_2B_TB.v
................\.....\DOC\fft64_um.pdf
................\.....\RTL\bufram64c1.v
................\.....\...\cnorm.v
................\.....\...\fft64_config.inc
................\.....\...\fft8.v
................\.....\...\mpu707.v
................\.....\...\ram2x64c_1.v
................\.....\...\ram64.v
................\.....\...\rotator64_v.v
................\.....\...\usfft64_2b.v
................\.....\...\WROM64.v
................\.....\BENCH
................\.....\DOC
................\.....\RTL
................\branches
................\tags
................\trunk
pipelined_fft_64

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