Welcome![Sign In][Sign Up]
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: seg71 Download
 Description: 7-segment test experiment 1: 8-bit dynamic digital scanning mode in the pipe " while" display 0- 7 experiment is introduced to the user multiple digital dynamic display method. Dynamic display method is to rotate at a certain frequency of the various digital control of the COM to send low end, while the corresponding data sent to each segment.
 Downloaders recently: [More information of uploader yuxiang_sun]
 To Search:
File list (Check if you may need any files):
seg71.v
    

CodeBus www.codebus.net