Title:
Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Ex
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Description: From ALTERA website. This document details how to use the MAX ® II CPLD to implement pulse width modulation (PWM). This design also uses the MAX II CPLD' s internal oscillator user flash memory, without using a special external clock. With verilog source.
- [bldcm] - Established by the brushless DC motor sy
- [Pwm] - cpld the PWM generation circuit, IGBT ca
- [bijiaoqi] - compare by vhdl ,use as changing sin to
- [rom] - Rom memory, based on simple and practica
- [FlashLock_test] - pdf actel fpga verilog FLASH write
- [hanzi] - VGA display Chinese characters in Verilo
File list (Check if you may need any files):
利用MAX II CPLD 实现 脉冲宽度调制.pdf
AN501_Pulse_Width_Modulator_Altera_MAX_II_CPLD_Design_Example\code\pwm_main.v
.............................................................\modelsim\pulse_width_modulator.cr.mti
.............................................................\........\pulse_width_modulator.mpf
.............................................................\........\pwm_main.v
.............................................................\........\pwm_sim.cr.mti
.............................................................\........\pwm_sim.mpf
.............................................................\........\test_pwm.v
.............................................................\........\wave.bmp
.............................................................\........\wave.do
.............................................................\........\wave2.bmp
.............................................................\........\wave2.do
.............................................................\........\wave3.bmp
.............................................................\........\wave3.do
.............................................................\........\wave4.bmp
.............................................................\........\wave4.do
.............................................................\........\wave5.bmp
.............................................................\........\wave5.do
.............................................................\........\.ork\altufm_osc0_altufm_osc_1p3\verilog.asm
.............................................................\........\....\..........................\_primary.dat
.............................................................\........\....\..........................\_primary.vhd
.............................................................\........\....\clkgen\verilog.asm
.............................................................\........\....\......\_primary.dat
.............................................................\........\....\......\_primary.vhd
.............................................................\........\....\..._gen\verilog.asm
.............................................................\........\....\.......\_primary.dat
.............................................................\........\....\.......\_primary.vhd
.............................................................\........\....\dutycycle\verilog.asm
.............................................................\........\....\.........\_primary.dat
.............................................................\........\....\.........\_primary.vhd
.............................................................\........\....\...._cycle\verilog.asm
.............................................................\........\....\..........\_primary.dat
.............................................................\........\....\..........\_primary.vhd
.............................................................\........\....\pwm_gen\verilog.asm
.............................................................\........\....\.......\_primary.dat
.............................................................\........\....\.......\_primary.vhd
.............................................................\........\....\....main\verilog.asm
.............................................................\........\....\........\_primary.dat
.............................................................\........\....\........\_primary.vhd
.............................................................\........\....\test_pwm\verilog.asm
.............................................................\........\....\........\_primary.dat
.............................................................\........\....\........\_primary.vhd
.............................................................\........\....\_info
.............................................................\quartus\db\pwm_main.db_info
.............................................................\.......\..\pwm_mai
