adder_fa4bit\bench\adder_4bit_tb.v
............\.....\adder_4bit_tb.v.bak
............\bench
............\rtl\fulladder_1bit.v
............\...\fulladder_1bit.v.bak
............\...\fulladder_4bit.v
............\...\fulladder_4bit.v.bak
............\...\halfadder_1bit.v
............\...\halfadder_1bit.v.bak
............\rtl
............\sim\adder4bit_by_1bit.cr.mti
............\...\adder4bit_by_1bit.mpf
............\...\vsim.wlf
............\...\wave.do
............\...\.ork\adder_4bit_tb\verilog.asm
............\...\....\.............\_primary.dat
............\...\....\.............\_primary.vhd
............\...\....\adder_4bit_tb
............\...\....\fulladder_1bit\verilog.asm
............\...\....\..............\_primary.dat
............\...\....\..............\_primary.vhd
............\...\....\fulladder_1bit
............\...\....\..........4bit\verilog.asm
............\...\....\..............\_primary.dat
............\...\....\..............\_primary.vhd
............\...\....\fulladder_4bit
............\...\....\halfadder_1bit\verilog.asm
............\...\....\..............\_primary.dat
............\...\....\..............\_primary.vhd
............\...\....\halfadder_1bit
............\...\....\_info
............\...\work
............\sim
adder_fa4bit