Description: Verilog language using any odd hardware divide, and the modelsim simulation testing using ise11.1
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div_any_nodd\.cxl.mti_se.version
............\.lso
............\compxlib.log
............\div_anyodd.cmd_log
............\div_anyodd.lso
............\div_anyodd.ngc
............\div_anyodd.ngr
............\div_anyodd.prj
............\div_anyodd.stx
............\div_anyodd.syr
............\div_anyodd.udo
............\div_anyodd.v
............\div_anyodd.xst
............\div_anyodd_summary.html
............\div_anyodd_wave.fdo
............\div_anyodd_xst.xrpt
............\div_any_nodd.gise
............\div_any_nodd.ise
............\div_any_nodd.ntrc_log
............\div_any_nodd.xise
............\............_xdb\cst.xbcd
............\................\tmp\ise\version
............\................\...\...\__OBJSTORE__\HierarchicalDesign\HDProject\HDProject
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............\................\...\...\............\PnAutoRun\Scripts\RunOnce_tcl
............\................\...\...\............\.........\.......\RunOnce_tcl_StrTbl
............\................\...\...\............\.rojectNavigator\dpm_project_main\dpm_project_main
............\................\...\...\............\................\................\dpm_project_main_StrTbl
............\................\...\...\............\................Gui\CViewSelector
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............\................\...\...\............\...................\File-SynthesisOnly
............\................\...\...\............\...................\File-SynthesisOnly_StrTbl
............\................\...\...\............\...................\Library-SynthesisOnly
............\................\...\...\............\...................\Library-SynthesisOnly_StrTbl
............\................\...\...\............\...................\Process-BehavioralSim-
............\................\...\...\............\...................\Process-BehavioralSim-DESUT_VERILOG
............\................\...\...\............\...................\Process-BehavioralSim-DESUT_VERILOG_StrTbl
............\................\...\...\............\...................\Process-BehavioralSim-_StrTbl
............\................\...\...\............\...................\Process-PostMapSim-
............\................\...\...\............\...................\Process-PostMapSim-_StrTbl
............\................\...\...\............\...................\Process-PostRouteSim-
............\................\...\...\............\...................\Process-PostRouteSim-_StrTbl
............\................\...\...\............\...................\Process-PostTransSim-
............\................\...\...\............\...................\Process-PostTransSim-_StrTbl
............\................\...\...\............\...................\Process-SynthesisOnly-
............\................\...\...\............\...................\Process-SynthesisOnly-DESUT_VERILOG
............\................\...\...\............\...................\Process-SynthesisOnly-DESUT_VERILOG_StrTbl
............\................\...\...\............\...................\Process-SynthesisOnly-_StrTbl
............\................\...\...\............\...................\Source-BehavioralSim-AutoCompile
............\................\...\...\............\...................\Source-BehavioralSim-AutoCompile_StrTbl
............\................\...\...\............\...................\Source-PostMapSim-AutoCompile
............\................\...\...\............\...................\Source-PostMapSim-AutoCompile_StrTbl
............\................\...\...\............\...................\Source-PostRouteSim-AutoCompile
............\................\...\...\............\...................\Source-PostRouteSim-AutoCompile_StrTbl
............\................\...\...\............\...................\Source-PostTransSim-AutoCompile
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