CPLD_MICROSTP_DRIVER\code
....................\....\implement
....................\....\.........\microstep_cheap.ucf
....................\....\src
....................\....\...\counter.vhd
....................\....\...\dac_translator.vhd
....................\....\...\dac_translator_parl.vhd
....................\....\...\Gate_Limiter.vhd
....................\....\...\Latch_SR.vhd
....................\....\...\microstep_cheap.bde
....................\PCB
....................\...\FPGA BASE MICROSTEP MAINV3.MAX
....................\...\FPGA BASE MICROSTEP MAINV3.PCBDOC
....................\schematic
....................\.........\f1.opj
....................\.........\FPGA_DRIVER.DBK
....................\.........\FPGA_DRIVER.DSN
....................\.........\FPGA_DRIVER.opj
....................\.........\layout.log
....................\.........\PAGE1.DXF