usb1.1\usb1.1\usb1_1_deviceip\testbench\tests.v
......\......\...............\.........\tests_lib.v
......\......\...............\.........\test_bench_top.v
......\......\...............\.........\timescale.v
......\......\...............\sim\sim1.txt
......\......\...............\...\sim2.txt
......\......\...............\...\sim3.txt
......\......\...............\RTL_code\timescale.v
......\......\...............\........\usb1_core.v
......\......\...............\........\usb1_crc16.v
......\......\...............\........\usb1_crc5.v
......\......\...............\........\usb1_ctrl.v
......\......\...............\........\usb1_defines.v
......\......\...............\........\usb1_fifo2.v
......\......\...............\........\usb1_idma.v
......\......\...............\........\usb1_pa.v
......\......\...............\........\usb1_pd.v
......\......\...............\........\usb1_pe.v
......\......\...............\........\usb1_pl.v
......\......\...............\........\usb1_rom1.v
......\......\...............\........\usb1_utmi_if.v
......\......\...............\doc\read_me_1.1.txt
......\......\...............\...\read_me_1.2.txt
......\......\...............\...\sucess_story.txt
......\......\USB1_1 PHY\timescale.v
......\......\..........\USB 1.1 PHY.txt
......\......\..........\usb_phy.v
......\......\..........\usb_rx_phy.v
......\......\..........\usb_tx_phy.v
......\......\usb1_1_deviceip\testbench
......\......\...............\sim
......\......\...............\RTL_code
......\......\...............\doc
......\......\usb1_1_deviceip
......\......\USB1_1 PHY
......\usb1.1
usb1.1