Description: The Xilinx V4FPGA digital clock administration module s first floor primitive realizes the code, on the hardware runs passes
- [BUFG_CLKDV_SUBM] - xilinx DCM applications, fully available
- [DCM] - Xilinx, a number of models developed ver
- [DA_fir_parrel] - FPGA implementation using VHDL program p
- [pingpang] - Table tennis simulation game, enter a ke
File list (Check if you may need any files):
dcm1\.lso
....\chip.cdc
....\dcm1.bgn
....\dcm1.bit
....\dcm1.bld
....\dcm1.cmd_log
....\dcm1.drc
....\dcm1.ise
....\dcm1.lso
....\dcm1.ncd
....\dcm1.ngc
....\dcm1.ngd
....\dcm1.ngr
....\dcm1.ntrc_log
....\dcm1.pad
....\dcm1.par
....\dcm1.pcf
....\dcm1.prj
....\dcm1.ptwx
....\dcm1.restore
....\dcm1.stx
....\dcm1.syr
....\dcm1.twr
....\dcm1.twx
....\dcm1.unroutes
....\dcm1.ut
....\dcm1.vhd
....\dcm1.xpi
....\dcm1.xst
....\dcm1_cs.blc
....\dcm1_cs.ngc
....\dcm1_guide.ncd
....\dcm1_map.map
....\dcm1_map.mrp
....\dcm1_map.ncd
....\dcm1_map.ngm
....\dcm1_map.xrpt
....\dcm1_ngdbuild.xrpt
....\dcm1_pad.csv
....\dcm1_pad.txt
....\dcm1_par.xrpt
....\dcm1_prev_built.ngd
....\dcm1_summary.html
....\dcm1_summary.xml
....\dcm1_usage.xml
....\dcm1_vhdl.prj
....\dcm1_xst.xrpt
....\device_usage_statistics.html
....\fangzhen.fdo
....\fangzhen.tdo
....\fangzhen.udo
....\fangzhen.vhd
....\fangzhen_wave.fdo
....\fangzhen_wave.tdo
....\pepExtractor.prj
....\transcript
....\user.ucf
....\vish_stacktrace.vstf
....\vsim.wlf
....\xlnx_auto_0.ise
....\_xmsgs\bitgen.xmsgs
....\......\map.xmsgs
....\......\netgen.xmsgs
....\......\ngdbuild.xmsgs
....\......\par.xmsgs
....\......\trce.xmsgs
....\......\xst.xmsgs
....\.ngo\dcm1_cs_signalbrowser.ngo
....\....\dcm1_cs_signalbrowser.ver
....\....\icon_pro.ncf
....\....\icon_pro.ngc
....\....\ila_pro_0.ncf
....\....\ila_pro_0.ngc
....\....\netlist.lst
....\....\cs_ila_pro_0\coregen.cgp
....\....\............\coregen.log
....\....\............\generate_ila_pro_0.xco
....\....\............\ila_pro_0.cdc
....\....\............\ila_pro_0.vhd
....\....\............\ila_pro_0.vho
....\....\............\ila_pro_0.xco
....\....\............\ila_pro_0_flist.txt
....\....\............\ila_pro_0_readme.txt
....\....\............\ila_pro_0_xmdf.tcl
....\....\............\xlnx_auto_0.ise
....\....\............\..........._xdb\tmp\ise.lock
....\....\............\...............\...\...\version
....\....\............\...............\...\...\__REGISTRY__\_ProjRepoInternal_\regkeys
....\....\............\...............\...\...\............\STE\regkeys
....\....\............\...............\...\...\............\...\xst\regkeys
....\....\............\...............\...\...\............\...\netgen\regkeys
....\....\............\...............\...\...\............\common\regkeys
....\....\............\...............\...\...\............\Autonym\regkeys
....\....\....con_pro\coregen.cgp
....\....\...........\coregen.log
....\....\...........\generate_icon_pro.xco
....\....\...........\icon_pro.vhd
....\....\...........\icon_pro.vho
....\....\...........\icon_pro.xco
....\....\...........\icon_pro_flist.txt
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