Description: The UART VHDL-based communication design: achieving between CPLD and the PC serial port (RS232) communications. PC CPLD can be continuously received 8-bit data and writes data to FIFO (first in first out memory), the receiver is complete CPLD then remove it from the FIFO 8-bit data to the PC.
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File list (Check if you may need any files):
UART_TVHDL\db\add_sub_5nh.tdf
..........\..\prev_cmp_UART_TVHDL.asm.qmsg
..........\..\prev_cmp_UART_TVHDL.fit.qmsg
..........\..\prev_cmp_UART_TVHDL.map.qmsg
..........\..\prev_cmp_UART_TVHDL.qmsg
..........\..\prev_cmp_UART_TVHDL.tan.qmsg
..........\..\UART_TVHDL.ae.hdb
..........\..\UART_TVHDL.asm.qmsg
..........\..\UART_TVHDL.cbx.xml
..........\..\UART_TVHDL.cmp.cdb
..........\..\UART_TVHDL.cmp.hdb
..........\..\UART_TVHDL.cmp.logdb
..........\..\UART_TVHDL.cmp.rdb
..........\..\UART_TVHDL.cmp.tdb
..........\..\UART_TVHDL.cmp0.ddb
..........\..\UART_TVHDL.db_info
..........\..\UART_TVHDL.eco.cdb
..........\..\UART_TVHDL.fit.qmsg
..........\..\UART_TVHDL.hier_info
..........\..\UART_TVHDL.hif
..........\..\UART_TVHDL.lpc.html
..........\..\UART_TVHDL.lpc.rdb
..........\..\UART_TVHDL.lpc.txt
..........\..\UART_TVHDL.map.cdb
..........\..\UART_TVHDL.map.hdb
..........\..\UART_TVHDL.map.logdb
..........\..\UART_TVHDL.map.qmsg
..........\..\UART_TVHDL.pre_map.cdb
..........\..\UART_TVHDL.pre_map.hdb
..........\..\UART_TVHDL.rpp.qmsg
..........\..\UART_TVHDL.rtlv.hdb
..........\..\UART_TVHDL.rtlv_sg.cdb
..........\..\UART_TVHDL.rtlv_sg_swap.cdb
..........\..\UART_TVHDL.sgate.rvd
..........\..\UART_TVHDL.sgate_sm.rvd
..........\..\UART_TVHDL.sgdiff.cdb
..........\..\UART_TVHDL.sgdiff.hdb
..........\..\UART_TVHDL.sld_design_entry.sci
..........\..\UART_TVHDL.sld_design_entry_dsc.sci
..........\..\UART_TVHDL.syn_hier_info
..........\..\UART_TVHDL.tan.qmsg
..........\..\UART_TVHDL.tis_db_list.ddb
..........\..\UART_TVHDL.tmw_info
..........\incremental_db\compiled_partitions\UART_TVHDL.root_partition.map.kpt
..........\..............\README
..........\UART.vhd
..........\UART.vhd.bak
..........\UART_FIFO.vhd
..........\UART_TVHDL.asm.rpt
..........\UART_TVHDL.cdf
..........\UART_TVHDL.done
..........\UART_TVHDL.dpf
..........\UART_TVHDL.fit.rpt
..........\UART_TVHDL.fit.summary
..........\UART_TVHDL.flow.rpt
..........\UART_TVHDL.map.rpt
..........\UART_TVHDL.map.summary
..........\UART_TVHDL.pin
..........\UART_TVHDL.pof
..........\UART_TVHDL.qpf
..........\UART_TVHDL.qsf
..........\UART_TVHDL.qws
..........\UART_TVHDL.tan.rpt
..........\UART_TVHDL.tan.summary
..........\UART_TVHDL.vhd
..........\UART_TVHDL.vhd.bak
..........\基于VHDL的UART通讯设计.docx
..........\incremental_db\compiled_partitions
..........\db
..........\incremental_db
UART_TVHDL
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