Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: SOU Download
 Description: It is written with C fixed-point data generate code sine function, the content is generated verilog RAM or ROM, and Matlab in the processing of the data used.
 Downloaders recently: [More information of uploader fxt972858213]
 To Search:
File list (Check if you may need any files): 
SOU.C

CodeBus www.codebus.net