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VHDL-FPGA-Verilog
Title:
convolution_encoder_VHDL
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Category:
VHDL-FPGA-Verilog
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[PDF]
File Size:
124kb
Update:
2012-11-26
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Uploaded by:
07211034
Description:
for 802.11a simulation WLAN FEC convolution_encoder g0=133 g1=171 Rate 0:1/2 1:2/3 2:3/4 for 802.11a simulation
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卷积码编译码的VHDL实现.pdf
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