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Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: dds Download
 Description: Dds with the Verilog language technology based on the cosine signal generator, the output bit width is 16 bits
 Downloaders recently: [More information of uploader heidabaiyuan]
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File list (Check if you may need any files): 
dds\dds.v
...\rom_cos.coe
...\rom_cose.xco
...\rom_sin.coe
...\rom_sine.xco
...\transcript
dds

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