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Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: EDKlab Download
 Description: This is my participation in the design competition this time with the fpga' s routine, may be useful for all
 To Search:
  • [edk_ctt] - fpga ise xilinx Low cost OEM and develop
File list (Check if you may need any files):
EDKlab\lab1\bitinit.log
......\....\.lkdiagram\svg10.dtd
......\....\..........\system.css
......\....\..........\system.html
......\....\..........\system.svg
......\....\clock_generator_0.log
......\....\data\system.ucf
......\....\etc\bitgen.ut
......\....\...\download.cmd
......\....\...\fast_runtime.opt
......\....\hdl\clock_generator_0_wrapper.vhd
......\....\...\debug_module_wrapper.vhd
......\....\...\dlmb_cntlr_wrapper.vhd
......\....\...\dlmb_wrapper.vhd
......\....\...\elaborate\lmb_bram_elaborate_v1_00_a\hdl\vhdl\lmb_bram_elaborate.vhd
......\....\...\ilmb_cntlr_wrapper.vhd
......\....\...\ilmb_wrapper.vhd
......\....\...\lmb_bram_wrapper.vhd
......\....\...\mb_plb_wrapper.vhd
......\....\...\microblaze_0_wrapper.vhd
......\....\...\micron_ram_util_bus_split_1_wrapper.vhd
......\....\...\micron_ram_wrapper.vhd
......\....\...\proc_sys_reset_0_wrapper.vhd
......\....\...\rs232_port_wrapper.vhd
......\....\...\system.vhd
......\....\...\system_stub.vhd
......\....\implementation\bitgen.ut
......\....\..............\cache\cache.cat
......\....\..............\.....\clock_generator_0_wrapper.ngc
......\....\..............\.....\debug_module_wrapper.ngc
......\....\..............\.....\dlmb_cntlr_wrapper.ngc
......\....\..............\.....\dlmb_wrapper.ngc
......\....\..............\.....\ilmb_cntlr_wrapper.ngc
......\....\..............\.....\ilmb_wrapper.ngc
......\....\..............\.....\lmb_bram_wrapper.ngc
......\....\..............\.....\mb_plb_wrapper.ngc
......\....\..............\.....\microblaze_0_wrapper.ngc
......\....\..............\.....\micron_ram_util_bus_split_1_wrapper.ngc
......\....\..............\.....\micron_ram_wrapper.ngc
......\....\..............\.....\proc_sys_reset_0_wrapper.ngc
......\....\..............\.....\rs232_port_wrapper.ngc
......\....\..............\clock_generator_0_wrapper.ngc
......\....\..............\clock_generator_0_wrapper.ngc_xst.xrpt
......\....\..............\clock_generator_0_wrapper_vhdl.prj
......\....\..............\debug_module_wrapper.ngc
......\....\..............\debug_module_wrapper.ngc_xst.xrpt
......\....\..............\debug_module_wrapper_vhdl.prj
......\....\..............\dlmb_cntlr_wrapper.ngc
......\....\..............\dlmb_cntlr_wrapper.ngc_xst.xrpt
......\....\..............\dlmb_cntlr_wrapper_vhdl.prj
......\....\..............\dlmb_wrapper.ngc
......\....\..............\dlmb_wrapper.ngc_xst.xrpt
......\....\..............\dlmb_wrapper_vhdl.prj
......\....\..............\download.bit
......\....\..............\fpga.flw
......\....\..............\ilmb_cntlr_wrapper.ngc
......\....\..............\ilmb_cntlr_wrapper.ngc_xst.xrpt
......\....\..............\ilmb_cntlr_wrapper_vhdl.prj
......\....\..............\ilmb_wrapper.ngc
......\....\..............\ilmb_wrapper.ngc_xst.xrpt
......\....\..............\ilmb_wrapper_vhdl.prj
......\....\..............\lmb_bram_wrapper.ngc
......\....\..............\lmb_bram_wrapper.ngc_xst.xrpt
......\....\..............\lmb_bram_wrapper_vhdl.prj
......\....\..............\mb_plb_wrapper.ngc
......\....\..............\mb_plb_wrapper.ngc_xst.xrpt
......\....\..............\mb_plb_wrapper_vhdl.prj
......\....\..............\microblaze_0_wrapper.ngc
......\....\..............\microblaze_0_wrapper.ngc_xst.xrpt
......\....\..............\microblaze_0_wrapper_vhdl.prj
......\....\..............\micron_ram_util_bus_split_1_wrapper.ngc
......\....\..............\micron_ram_util_bus_split_1_wrapper.ngc_xst.xrpt
......\....\..............\micron_ram_util_bus_split_1_wrapper_vhdl.prj
......\....\..............\micron_ram_wrapper.ngc
......\....\..............\micron_ram_wrapper.ngc_xst.xrpt
......\....\..............\micron_ram_wrapper_vhdl.prj
......\....\..............\netlist.lst
......\....\..............\proc_sys_reset_0_wrapper.ngc
......\....\..............\proc_sys_reset_0_wrapper.ngc_xst.xrpt
......\....\..............\proc_sys_reset_0_wrapper_vhdl.prj
......\....\..............\rs232_port_wrapper\rs232_port_wrapper.ngc
......\....\..............\..................\xlnx_auto_0.ise
......\....\..............\rs232_

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