Description: For achieving a 50 duty cycle frequency N times the odd, the first rising edge trigger to die for N counts, count to a particular value of n, the output clock flip, and then count (N-1)/2 times Flip again to get a 50 duty cycle odd number n of non-frequency clock. Similarly, at the same time falling edge-triggered mode N counts, so count to n, the output clock flip, the same re-count (N-1)/2 times the output clock duty cycle once again turn generates 50 of non- n odd clock frequency. Two 50 duty cycle n non-frequency clock phase or operation, or get 50 duty cycle for the odd-N frequency clock.
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在FPGA中实现奇数分频.doc
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