LIP6301CORE_tv_filter\Logical Intellectual Properity  Core_1.pdf
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.....................\...\core
.....................\...\deb.do
.....................\...\deb.do%
.....................\...\debug.do
.....................\...\debugtg.do
.....................\...\esdram.bmp
.....................\...\esdram.img
.....................\...\go_compile
.....................\...\go_compile.txt
.....................\...\modelsim.ini
.....................\...\newTFImgSz.TXT
.....................\...\orgTFImgSz.TXT
.....................\...\temp
.....................\...\temp.txt
.....................\...\TEST_EVEN.TXT
.....................\...\TFclock.TXT
.....................\...\TFImgSz.bak
.....................\...\TFImgSz.TXT
.....................\...\TFLB1WRT.TXT
.....................\...\TFLB2WRT.TXT
.....................\...\TFMISC.TXT
.....................\...\TFOB1WRT.TXT
.....................\...\TFOB2WRT.TXT
.....................\...\TFOBWRT_EVEN.TXT
.....................\...\TFOBWRT_EVEN.TXT%
.....................\...\TFOBWRT_ODD.TXT
.....................\...\TFOBWRT_ODD.TXT%
.....................\...\TFpixel.log
.....................\...\TFPixel.TXT
.....................\...\TFRegister.TXT
.....................\...\transcript
.....................\...\TVFilter.bmp
.....................\...\TVFilter.img
.....................\...\vcom_tvf
.....................\...\vcom_tvf%
.....................\...\vcom_tvf2
.....................\...\vcom_tvf2%
.....................\...\~$OBWRT_EVEN.TXT
.....................\.rc\bak\ram400x24.vhdl
.....................\...\...\ram400x36.vhdl
.....................\...\...\tb_tfctrl.vhdl
.....................\...\...\tfctrl_arc_d.vhdl
.....................\...\...\tfctrl_cfg.vhdl
.....................\...\...\tfctrl_ent.vhdl
.....................\...\...\tfdp_arc_d.vhdl
.....................\...\...\tfdp_cfg.vhdl
.....................\...\...\tfdp_ent.vhdl
.....................\...\...\tflb_arc_d.vhdl
.....................\...\...\tflb_cfg.vhdl
.....................\...\...\tflb_ent.vhdl
.....................\...\...\tfmac_arc_d.vhdl
.....................\...\...\tfmac_cfg.vhdl
.....................\...\...\tfmac_ent.vhdl
.....................\...\...\tfmult_arc_d.vhdl
.....................\...\...\tfmult_cfg.vhdl
.....................\...\...\tfmult_ent.vhdl
.....................\...\...\tfob_arc_d.vhdl
.....................\...\...\tfob_cfg.vhdl
.....................\...\...\tfob_ent.vhdl
.....................\...\...\tfram800x24_arc_d.vhdl
.....................\...\...\tfram800x24_cfg.vhdl
.....................\...\...\tfram800x24_ent.vhdl
.....................\...\...\tfram800x36_arc_d.vhdl
.....................\...\...\tfram800x36_cfg.vhdl
.....................\...\...\tfram800x36_ent.vhdl
.....................\...\...\tfreg_arc_d.vhdl
.....................\...\...\tfreg_cfg.vhdl
.....................\...\...\tfreg_ent.vhdl
.....................\...\...\tftg_arc_d.vhdl
.....................\...\...\tftg_cfg.vhdl
.....................\...\...\tftg_ent.vhdl
.....................\...\...\tftg_test.vhdl
.....................\...\...\tfunit.f
.....................\...\...\tfunit_arc_d.vhdl
.....................\...\...\tfunit_cfg.vhdl
.....................\...\...\tfunit_ent.vhdl
.....................\...\...\tfunit_mas.doc
.....................\...\control.vhdl
.....................\...\dif_tfctrl_ent
.....................\...\hot.vhdl
.....................\...\tb_tfctrl.vhdl
.....................\...\temp
.....................\...\tfctrl_arc_d.vhdl
.....................\...\tfctrl_cfg.vhdl
.....................\...\tfctrl_ent.vhdl
.....................\...\tfdda_arc_d.vhdl
.....................\...\tfdda_cfg.vhdl
.....................\...\tfdda_ent.vhdl
.....................\...\tfdp_arc_d.vhdl
.....................\...\tfdp_cfg.vhdl
.....................\...\tfdp_ent.vhdl
.....................\...\tflb_arc_d.vhdl
.....................\...\tflb_cfg.vhdl
.....................\...\tflb_ent.vhdl
.....................\...\tfmac_arc_d.vhdl
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