Welcome![Sign In][Sign Up]
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: xiaoshufenpin_VHDL Download
 Description: Based on pre-N/N+1 divider fractional basic principles, and based on this principle, a decimal divider of the source code, by the bit width of the data given in this paper integral part of the scope of the code coefficients 0-15, For larger values can modify the code.
 Downloaders recently: [More information of uploader yangsenyuany]
 To Search:
  • [clock_divider] - Generate arbitrary decimal divider princ
  • [conformPulse] - The program realization of two-phase hyb
  • [12dac] - a 12bit dac need a lpf which can view cl
  • [FPGA-DEVIDER] - FPGA-based implementation of the fractio
  • [X] - X
File list (Check if you may need any files):
xiaoshufenpin_VHDL.doc
    

CodeBus www.codebus.net