Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: system05_latest.tar Download
 Description: 6805 compatible CPU Core 6805 compatible core - 4 x 8 bit Parallel I/O ports - Dual 8 bit Timer - MiniUART compatible with 6850 ACIA. - Runs with an E clock of 12.5MHz and system clock of 25MHz
 Downloaders recently: [More information of uploader amin_rohani61]
 To Search:
File list (Check if you may need any files): 
46383150system05_latest.tar

CodeBus www.codebus.net