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VHDL-FPGA-Verilog
Title:
eth_send
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Category:
VHDL-FPGA-Verilog
Tags:
[VHDL]
[源码]
File Size:
4kb
Update:
2012-11-26
Downloads:
0 Times
Uploaded by:
liuchenghua0131
Description:
Tsinghua University sdr project, network interface code. Verilog preparation. Very practical. Hope you like it.
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verilog_cordic.tar
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eth_send.v
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