Description: Completion of a binary full subtracter design, implementation, respectively, using the text input method, hierarchical design, are based on half adder and logic gates.
To Search:
- [qjqsj] - VHDL description of the structure design
- [qwrrtwt] - Try to design a whole by a binary number
File list (Check if you may need any files):
EDA1\db\fullsub.asm.qmsg
....\..\fullsub.cbx.xml
....\..\fullsub.cmp.cdb
....\..\fullsub.cmp.hdb
....\..\fullsub.cmp.logdb
....\..\fullsub.cmp.rdb
....\..\fullsub.cmp.tdb
....\..\fullsub.cmp0.ddb
....\..\fullsub.db_info
....\..\fullsub.eco.cdb
....\..\fullsub.eds_overflow
....\..\fullsub.fit.qmsg
....\..\fullsub.fnsim.hdb
....\..\fullsub.fnsim.qmsg
....\..\fullsub.hier_info
....\..\fullsub.hif
....\..\fullsub.lpc.html
....\..\fullsub.lpc.rdb
....\..\fullsub.lpc.txt
....\..\fullsub.map.cdb
....\..\fullsub.map.hdb
....\..\fullsub.map.logdb
....\..\fullsub.map.qmsg
....\..\fullsub.pre_map.cdb
....\..\fullsub.pre_map.hdb
....\..\fullsub.rtlv.hdb
....\..\fullsub.rtlv_sg.cdb
....\..\fullsub.rtlv_sg_swap.cdb
....\..\fullsub.sgdiff.cdb
....\..\fullsub.sgdiff.hdb
....\..\fullsub.sim.cvwf
....\..\fullsub.sim.hdb
....\..\fullsub.sim.qmsg
....\..\fullsub.sim.rdb
....\..\fullsub.simfam
....\..\fullsub.sld_design_entry.sci
....\..\fullsub.sld_design_entry_dsc.sci
....\..\fullsub.syn_hier_info
....\..\fullsub.tan.qmsg
....\..\fullsub.tis_db_list.ddb
....\..\fullsub.tmw_info
....\..\prev_cmp_fullsub.asm.qmsg
....\..\prev_cmp_fullsub.fit.qmsg
....\..\prev_cmp_fullsub.map.qmsg
....\..\prev_cmp_fullsub.qmsg
....\..\prev_cmp_fullsub.sim.qmsg
....\..\prev_cmp_fullsub.tan.qmsg
....\..\wed.wsf
....\fullsub.asm.rpt
....\fullsub.done
....\fullsub.dpf
....\fullsub.fit.rpt
....\fullsub.fit.summary
....\fullsub.flow.rpt
....\fullsub.map.rpt
....\fullsub.map.summary
....\fullsub.pin
....\fullsub.pof
....\fullsub.qpf
....\fullsub.qsf
....\fullsub.qws
....\fullsub.sim.rpt
....\fullsub.sof
....\fullsub.tan.rpt
....\fullsub.tan.summary
....\fullsub.txt
....\fullsub.vhd
....\fullsub.vwf
....\halfsub.txt
....\halfsub.vhd
....\incremental_db\compiled_partitions\fullsub.root_partition.map.kpt
....\..............\README
....\orgate.txt
....\orgate.vhd
....\仿真\QQ截图未命名6.jpg
....\....\仿真图.jpg
....\....\波形.jpg
....\....\波形0.jpg
....\....\波形1.jpg
....\....\波形2.jpg
....\....\波形3.jpg
....\....\波形4.jpg
....\....\波形5.jpg
....\....\波形7.jpg
....\incremental_db\compiled_partitions
....\db
....\incremental_db
....\仿真
EDA1
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