Welcome![Sign In][Sign Up]
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: sin Download
 Description: Verilog function based on the simple and practical choice for beginners is a good material
 To Search:
File list (Check if you may need any files):
sin\ROM.V
...\sin.ise
...\sin.ntrc_log
...\sin.restore
...\sin_top.cmd_log
...\sin_top.lso
...\sin_top.prj
...\sin_top.syr
...\SIN_TOP.V
...\sin_top.xst
...\sin_top_summary.html
...\sin_top_TB.v
...\sin_top_xst.xrpt
...\xst\work\hdllib.ref
...\...\....\vlg3A\rom.bin
...\...\....\...28\sin__top.bin
...\...\dump.xst\sin_top.prj\ntrc.scr
...\...\........\...........\.gx\opt
...\...\........\...........\...\notopt
...\...\........\...........\ngx
...\...\work\vlg3A
...\...\....\vlg28
...\...\dump.xst\sin_top.prj
...\...\work
...\...\projnav.tmp
...\...\dump.xst
...\sin_xdb\tmp
...\xst
...\sin_xdb
sin
    

CodeBus www.codebus.net