Description: xilinx SP605 development board DCM module validation program, coreGen tool to generate nuclear DCM, completed by the DCM clock divider, frequency, and shift operations equal
- [dcm] - I was learning VHDL language, bought a s
- [HowtosimulateIPCore] - IP core generator generate ip after two
File list (Check if you may need any files):
DCM\auto_project.ipf
...\auto_project_1.ipf
...\DCM.gise
...\dcm.ipf
...\DCM.ise
...\DCM.xise
...\dcm_cs.cdc
...\dcm_tb.ucf
...\dcm_tb.v
...\dcm_tb_beh.prj
...\dcm_tb_isim_beh.exe
...\dcm_tb_isim_beh.wdb
...\dcm_tb_isim_beh1.wdb
...\dcm_tb_stx.prj
...\dcm_top.bgn
...\dcm_top.bit
...\dcm_top.bld
...\dcm_top.cmd_log
...\dcm_top.cpj
...\dcm_top.drc
...\dcm_top.lso
...\dcm_top.ncd
...\dcm_top.ngc
...\dcm_top.ngd
...\dcm_top.ngr
...\dcm_top.pad
...\dcm_top.par
...\dcm_top.pcf
...\dcm_top.prj
...\dcm_top.ptwx
...\dcm_top.stx
...\dcm_top.syr
...\dcm_top.twr
...\dcm_top.twx
...\dcm_top.unroutes
...\dcm_top.ut
...\dcm_top.v
...\dcm_top.xpi
...\dcm_top.xst
...\dcm_top_clkrgnrpt.xrpt
...\dcm_top_cs.blc
...\dcm_top_cs.ngc
...\dcm_top_guide.ncd
...\dcm_top_isim_beh.exe
...\dcm_top_isim_beh.wdb
...\dcm_top_map.map
...\dcm_top_map.mrp
...\dcm_top_map.ncd
...\dcm_top_map.ngm
...\dcm_top_map.xrpt
...\dcm_top_ngdbuild.xrpt
...\dcm_top_pad.csv
...\dcm_top_pad.txt
...\dcm_top_par.xrpt
...\dcm_top_stx.prj
...\dcm_top_summary.html
...\dcm_top_summary.xml
...\dcm_top_usage.xml
...\dcm_top_xst.xrpt
...\DCM_xdb\cst.xbcd
...\.......\tmp\ise\version
...\.......\...\...\__OBJSTORE__\HierarchicalDesign\HDProject\HDProject
...\.......\...\...\............\..................\.........\HDProject_StrTbl
...\.......\...\...\............\PnAutoRun\Scripts\RunOnce_tcl
...\.......\...\...\............\.........\.......\RunOnce_tcl_StrTbl
...\.......\...\...\............\.rojectNavigator\dpm_project_main\dpm_project_main
...\.......\...\...\............\................\................\dpm_project_main_StrTbl
...\.......\...\...\............\................Gui\CSourceProcessView
...\.......\...\...\............\...................\CSourceProcessView_StrTbl
...\.......\...\...\............\...................\CViewSelector
...\.......\...\...\............\...................\CViewSelector_StrTbl
...\.......\...\...\............\...................\File-SynthesisOnly
...\.......\...\...\............\...................\File-SynthesisOnly_StrTbl
...\.......\...\...\............\...................\Library-SynthesisOnly
...\.......\...\...\............\...................\Library-SynthesisOnly_StrTbl
...\.......\...\...\............\...................\Process-BehavioralSim-
...\.......\...\...\............\...................\Process-BehavioralSim-DESUT_VERILOG
...\.......\...\...\............\...................\Process-BehavioralSim-DESUT_VERILOG_StrTbl
...\.......\...\...\............\...................\Process-BehavioralSim-DESUT_XCO
...\.......\...\...\............\...................\Process-BehavioralSim-DESUT_XCO_StrTbl
...\.......\...\...\............\...................\Process-BehavioralSim-_StrTbl
...\.......\...\...\............\...................\Process-PostRouteSim-DESUT_VERILOG
...\.......\...\...\............\...................\Process-PostRouteSim-DESUT_VERILOG_StrTbl
...\.......\...\...\............\...................\Process-SynthesisOnly-
...\.......\...\...\............\...................\Process-SynthesisOnly-DESUT_CDC
...\.......\...\...\............\...................\Process-SynthesisOnly-DESUT_CDC_StrTbl
...\.......\...\...\............\...................\Process-SynthesisOnly-DESUT_UCF
...\.......\...\...\............\...................\Process-SynthesisOnly-DESUT_UCF_StrTbl
...\.......\...\...\............\...................\Process-SynthesisOnly-DESUT_VERILOG
...\.......\...\...\............\...................\Process-SynthesisOnly-DESUT_VERILOG_StrTbl
...\.......\...\...\............\...................\Process-SynthesisOnly-DESUT_XCO
...\.......\...\...\............\...................\Process-SynthesisOnly-DESUT_XCO_StrTbl
...\.......\...\...\............\...................\Process-SynthesisOnly-_StrTbl
...\.......\...\...\............\...................\Source-BehavioralSim-AutoCompile
...\.......\...\...\............\...................\Source-BehavioralSim-AutoCompile_StrTbl
...\.......\...\...\............\...................\Source-PostRouteSim-AutoCompile
...\.......\...\...\............\...................\
Download