Description: This source package is I2C bus model based on Verilog language. It has the following 4 parts: RTL code, testbench, sofeware simulating code, help document.
To Search:
- [sell] - CLK: standard clock signal, in this case
- [mt1389d] - MTK_DVD 1389D source code
- [SD_Controller_Verilog] - This source package is the SD card and M
- [register] - Verilog language used to write a simple
File list (Check if you may need any files):
I2C_Verilog_Model\bench\verilog\i2c_slave_model.v
.................\.....\.......\spi_slave_model.v
.................\.....\.......\tst_bench_top.v
.................\.....\.......\wb_master_model.v
.................\doc\i2c_specs.pdf
.................\rtl\verilog\i2c_master_bit_ctrl.v
.................\...\.......\i2c_master_byte_ctrl.v
.................\...\.......\i2c_master_defines.v
.................\...\.......\i2c_master_top.v
.................\...\.......\timescale.v
.................\sim\i2c_verilog\run\bench.vcd
.................\...\...........\...\ncverilog.key
.................\...\...........\...\ncverilog.log
.................\...\...........\...\run
.................\...\...........\...\INCA_libs
.................\...\...........\...\waves
.................\...\...........\run
.................\bench\verilog
.................\rtl\verilog
.................\sim\i2c_verilog
.................\bench
.................\doc
.................\rtl
.................\sim
I2C_Verilog_Model
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