Description: This based on Xilinx FPGA using VHDL implementation of the FIFO, has been transferred through, can be directly run.
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File list (Check if you may need any files):
VHD\blk1024high.ngc
...\blk1024high.xco
...\blk1024low.ngc
...\blk1024low.xco
...\control_registers.vhd
...\cos1024high.coe
...\cos1024low.coe
...\cossin32b.vhd
...\dmulti14x18p3.ngc
...\dmulti14x18p3.xco
...\dmulti18x18p3.ngc
...\dmulti18x18p3.xco
...\drfm01top.ucf
...\drfm01top.vhd
...\h_s_1.bit
...\h_s_10127.mcs
...\h_s_10127.prm
...\h_s_10127.sig
...\mcu_memmap.vhd
...\spi.vhd
...\wpan_mcuinf.vhd
...\xcarrier.vhd
VHD
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