422\FPGA板\22CY1C6封装库.PcbLib
...\......\22CY1C6封装库.pcblib_viewstate
...\......\422\422(bak).vwf
...\......\...\422-1232.bsf
...\......\...\422-bak.pin
...\......\...\422.asm.rpt
...\......\...\422.bdf
...\......\...\422.bsf
...\......\...\422.cdf
...\......\...\422.done
...\......\...\422.dpf
...\......\...\422.fit.rpt
...\......\...\422.fit.smsg
...\......\...\422.fit.summary
...\......\...\422.flow.rpt
...\......\...\422.map.rpt
...\......\...\422.map.summary
...\......\...\422.pin
...\......\...\422.pof
...\......\...\422.qpf
...\......\...\422.qsf
...\......\...\422.qws
...\......\...\422.sim.rpt
...\......\...\422.sof
...\......\...\422.tan.rpt
...\......\...\422.tan.summary
...\......\...\422.vwf
...\......\...\422_assignment_defaults.qdf
...\......\...\422_tmp_archive.qarlog
...\......\...\alog.bdf
...\......\...\alog.bsf
...\......\...\bxing7.bsf
...\......\...\bxing7.vhd
...\......\...\bxing_2byte.bsf
...\......\...\bxing_2byte.vhd
...\......\...\CLK100F.bsf
...\......\...\clk100F.VHD
...\......\...\CLK2000F.bsf
...\......\...\CLK2000F.vhd
...\......\...\CLK250F.bsf
...\......\...\CLK_6F.bsf
...\......\...\clk_6f.vhd
...\......\...\clockdiff250.bsf
...\......\...\clockdiff250.vhd
...\......\...\clockdiff4.bsf
...\......\...\clockdiff5.bsf
...\......\...\db\422.db_info
...\......\...\..\422.eco.cdb
...\......\...\..\422.sim.cvwf
...\......\...\..\422.sim.vwf
...\......\...\..\422.sld_design_entry.sci
...\......\...\..\prev_cmp_422.asm.qmsg
...\......\...\..\prev_cmp_422.fit.qmsg
...\......\...\..\prev_cmp_422.map.qmsg
...\......\...\..\prev_cmp_422.qmsg
...\......\...\..\prev_cmp_422.tan.qmsg
...\......\...\..\wed.wsf
...\......\...\..\wed.zsf
...\......\...\ES.bdf
...\......\...\ES.bsf
...\......\...\judge.bsf
...\......\...\judge.vhd
...\......\...\sendout_2byte.bsf
...\......\...\sendout_2byte.vhd
...\......\...\sendout_3byte.bsf
...\......\...\sendout_3byte.vhd
...\......\...\sopc_builder_debug_log.txt
...\......\...\time.bdf
...\......\...\time.bsf
...\......\...\timing1.bsf
...\......\...\timing1.vhd
...\......\...\timing3.bsf
...\......\...\timing3.vhd
...\......\...\trans3.bdf
...\......\...\trans3.bsf
...\......\...\trans7.bdf
...\......\...\trans7.bsf
...\......\Design Rule Check - FPGA开发板.drc
...\......\Design Rule Check - FPGA开发板.html
...\......\ding.PCBLIB
...\......\ding.pcblib_viewstate
...\......\FPGA422.SchDoc
...\......\FPGA422_b.SchDoc
...\......\FPGAPCB板 PCB ECO 2009-7-10 AM 10-00-39.LOG
...\......\FPGAPCB板 PCB ECO 2009-7-12 PM 05-47-01.LOG
...\......\FPGAPCB板 PCB ECO 2009-7-12 PM 05-59-40.LOG
...\......\FPGAPCB板 PCB ECO 2009-7-12 PM 08-44-31.LOG
...\......\FPGAPCB板 PCB ECO 2009-7-12 PM 08-45-10.LOG
...\......\FPGAPCB板 PCB ECO 2009-7-12 PM 08-46-26.LOG
...\......\FPGAPCB板 PCB ECO 2009-7-12 PM 08-47-12.LOG
...\......\FPGAPCB板 PCB ECO 2009-7-9 PM 09-28-39.LOG
...\......\FPGAPCB板 PCB ECO 2009-7-9 PM 09-45-36.LOG
...\......\FPGAPCB板 PCB ECO 2009-7-9 PM 10-12-43.LOG
...\......\FPGAPCB板.PcbDoc
...\......\FPGAPCB板.pcbdoc_viewstate
...\......\FPGAPCB板1.PcbDoc
...\......\FPGAPCB板1.pcbdoc_viewstate
...\......\FPGA开发板.pcb
...\......\FPGA开发板.pcb.htm
...\......\FPGA开发板.pcbdoc_viewstate