Description: ad conversion, using the Altera Cyclone FPGA (EP1C6-PQ240) chip, in QuartusII 9.0 compiler, a better reference value, has been tested.
- [dds] - Based on VHDL+ FPGA design of the DDS si
- [FPGAAD] - FPGA control AD procedure
- [EP1C6_EP1C12] - the minimum system of Altera FPGA EP1C6
- [AD] - FPGA control module of the AD7321 is per
- [Mars-EP1C6-F_code1] - In this package for the FPGA board to st
- [FPGA_AD] - Cyclone EP1C6240C8 FPGA-based interface
- [memtest] - In the digital system, there are many ch
- [42pcb] - The project is an FPGA development board
- [mcu-fpga] - Catalog FPGA & MCU Development Board
- [Cyclone-FPGA-Family-Data-Sheet] - Cyclone FPGA Family Data Sheet. Altera a
File list (Check if you may need any files):
da1_test\da1_test.asm.rpt
........\da1_test.done
........\da1_test.fit.rpt
........\da1_test.fit.smsg
........\da1_test.fit.summary
........\da1_test.flow.rpt
........\da1_test.map.rpt
........\da1_test.map.summary
........\da1_test.pin
........\da1_test.pof
........\da1_test.qpf
........\da1_test.qsf
........\da1_test.qws
........\da1_test.sof
........\da1_test.tan.rpt
........\da1_test.tan.summary
........\.b\da1_test.asm.qmsg
........\..\da1_test.cbx.xml
........\..\da1_test.cmp.bpm
........\..\da1_test.cmp.cdb
........\..\da1_test.cmp.ecobp
........\..\da1_test.cmp.hdb
........\..\da1_test.cmp.kpt
........\..\da1_test.cmp.logdb
........\..\da1_test.cmp.rdb
........\..\da1_test.cmp.tdb
........\..\da1_test.cmp0.ddb
........\..\da1_test.cmp_merge.kpt
........\..\da1_test.db_info
........\..\da1_test.eco.cdb
........\..\da1_test.fit.qmsg
........\..\da1_test.hier_info
........\..\da1_test.hif
........\..\da1_test.lpc.html
........\..\da1_test.lpc.rdb
........\..\da1_test.lpc.txt
........\..\da1_test.map.bpm
........\..\da1_test.map.cdb
........\..\da1_test.map.ecobp
........\..\da1_test.map.hdb
........\..\da1_test.map.kpt
........\..\da1_test.map.logdb
........\..\da1_test.map.qmsg
........\..\da1_test.map_bb.cdb
........\..\da1_test.map_bb.hdb
........\..\da1_test.map_bb.logdb
........\..\da1_test.pre_map.cdb
........\..\da1_test.pre_map.hdb
........\..\da1_test.rtlv.hdb
........\..\da1_test.rtlv_sg.cdb
........\..\da1_test.rtlv_sg_swap.cdb
........\..\da1_test.sgdiff.cdb
........\..\da1_test.sgdiff.hdb
........\..\da1_test.sld_design_entry.sci
........\..\da1_test.sld_design_entry_dsc.sci
........\..\da1_test.syn_hier_info
........\..\da1_test.tan.qmsg
........\..\da1_test.tis_db_list.ddb
........\..\da1_test.tmw_info
........\..\da1_test_global_asgn_op.abo
........\..\prev_cmp_da1_test.asm.qmsg
........\..\prev_cmp_da1_test.fit.qmsg
........\..\prev_cmp_da1_test.map.qmsg
........\..\prev_cmp_da1_test.qmsg
........\..\prev_cmp_da1_test.tan.qmsg
........\incremental_db\compiled_partitions\da1_test.root_partition.cmp.atm
........\..............\...................\da1_test.root_partition.cmp.dfp
........\..............\...................\da1_test.root_partition.cmp.hdbx
........\..............\...................\da1_test.root_partition.cmp.kpt
........\..............\...................\da1_test.root_partition.cmp.logdb
........\..............\...................\da1_test.root_partition.cmp.rcf
........\..............\...................\da1_test.root_partition.map.atm
........\..............\...................\da1_test.root_partition.map.dpi
........\..............\...................\da1_test.root_partition.map.hdbx
........\..............\...................\da1_test.root_partition.map.kpt
........\..............\README
........\topdesign.v
........\topdesign.v.bak
........\incremental_db\compiled_partitions
........\db
........\incremental_db
da1_test
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