Welcome![Sign In][Sign Up]
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: digital_clock Download
 Description: The program features include clock counting, adjustable, on the hour when time, etc. For beginners of FPGA with very useful shoes. Program himself write, and test, no problem. Chip uses is cyclone3
 To Search:
File list (Check if you may need any files):
数字钟 三\clkreport.bsf
.........\clkreport.inc
.........\clkreport.vhd
.........\clkreport.vhd.bak
.........\control.bsf
.........\control.vhd
.........\control.vhd.bak
.........\count10.bsf
.........\count10.vhd
.........\count10.vhd.bak
.........\count12.bsf
.........\count12.vhd
.........\count12.vhd.bak
.........\count24.bsf
.........\count24.vhd
.........\count24.vhd.bak
.........\count6.bsf
.........\count6.vhd
.........\count6.vhd.bak
.........\count7.bsf
.........\count7.vhd
.........\count7.vhd.bak
.........\db\dgclock.db_info
.........\..\dgclock.eco.cdb
.........\..\dgclock.sim.cvwf
.........\..\dgclock.sld_design_entry.sci
.........\..\dgclock_global_asgn_op.abo
.........\..\mux_3nc.tdf
.........\..\mux_joc.tdf
.........\..\mux_umc.tdf
.........\..\prev_cmp_dgclock.asm.qmsg
.........\..\prev_cmp_dgclock.fit.qmsg
.........\..\prev_cmp_dgclock.map.qmsg
.........\..\prev_cmp_dgclock.qmsg
.........\..\prev_cmp_dgclock.tan.qmsg
.........\..\wed.wsf
.........\decoder.bsf
.........\decoder.vhd
.........\decoder.vhd.bak
.........\dgclock.asm.rpt
.........\dgclock.bdf
.........\dgclock.done
.........\dgclock.dpf
.........\dgclock.fit.rpt
.........\dgclock.fit.smsg
.........\dgclock.fit.summary
.........\dgclock.flow.rpt
.........\dgclock.map.rpt
.........\dgclock.map.summary
.........\dgclock.pin
.........\dgclock.pof
.........\dgclock.qpf
.........\dgclock.qsf
.........\dgclock.qws
.........\dgclock.sim.rpt
.........\dgclock.sof
.........\dgclock.tan.rpt
.........\dgclock.tan.summary
.........\dgclock.vwf
.........\dgclock_assignment_defaults.qdf
.........\fpq.bsf
.........\fpq.vhd
.........\fpq.vhd.bak
.........\h_output.bsf
.........\h_output.vhd
.........\h_output.vhd.bak
.........\incremental_db\compiled_partitions\dgclock.root_partition.cmp.atm
.........\..............\...................\dgclock.root_partition.cmp.dfp
.........\..............\...................\dgclock.root_partition.cmp.hdbx
.........\..............\...................\dgclock.root_partition.cmp.kpt
.........\..............\...................\dgclock.root_partition.cmp.logdb
.........\..............\...................\dgclock.root_partition.cmp.rcf
.........\..............\...................\dgclock.root_partition.map.atm
.........\..............\...................\dgclock.root_partition.map.dpi
.........\..............\...................\dgclock.root_partition.map.hdbx
.........\..............\...................\dgclock.root_partition.map.kpt
.........\..............\README
.........\mux21.bsf
.........\mux21.vhd
.........\mux21.vhd.bak
.........\selec.bsf
.........\selec.vhd
.........\selec.vhd.bak
.........\incremental_db\compiled_partitions
.........\db
.........\incremental_db
数字钟 三
    

CodeBus www.codebus.net