Welcome![Sign In][Sign Up]
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: uart- Download
 Description: UART Universal Asynchronous communication engineering documents, ISE open the project, which has VERILOG source code can be compiled
 Downloaders recently: [More information of uploader chengma2006]
 To Search:
File list (Check if you may need any files):
UART
....\automake.log
....\baudrate_generator.jhd
....\baudrate_generator.vhd
....\baudrate_generator_TB.jhd
....\baudrate_generator_TB.vhd
....\counter.jhd
....\counter.vhd
....\counter_TB.jhd
....\counter_TB.vhd
....\detector.jhd
....\detector.vhd
....\detector_TB.jhd
....\detector_TB.vhd
....\parity_verifier.jhd
....\parity_verifier.vhd
....\parity_verifier_TB.jhd
....\parity_verifier_TB.vhd
....\shift_register.jhd
....\shift_register.vhd
....\shift_register_TB.jhd
....\shift_register_TB.vhd
....\switch.jhd
....\switch.vhd
....\switch_bus.jhd
....\switch_bus.vhd
....\switch_bus_TB.jhd
....\switch_bus_TB.vhd
....\transcript
....\UART.ise
....\UART.npl
....\uart_core.jhd
....\uart_core.vhd
....\UART_PACKAGE.vhd
....\uart_top.jhd
....\uart_top.vhd
....\uart_top_tb.jhd
....\uart_top_tb.vhd
....\UART_xdb
....\........\tmp
....\........\...\ise
....\........\...\ise.lock
....\........\...\...\version
....\........\...\...\__OBJSTORE__
....\........\...\...\............\Autonym
....\........\...\...\............\common
....\........\...\...\............\_ProjRepoInternal_
....\........\...\...\__REGISTRY__
....\........\...\...\............\Autonym
....\........\...\...\............\.......\regkeys
....\........\...\...\............\common
....\........\...\...\............\......\regkeys
....\........\...\...\............\_ProjRepoInternal_
....\........\...\...\............\..................\regkeys
....\........\...\npl
....\__projnav
....\__projnav.log
....\.........\p00p5000.kis
....\.........\p00pi000.kis
....\.........\p00pl000.kis
....\.........\runXst_tcl.rsp
使用说明.txt
    

CodeBus www.codebus.net