Description: implement the CPU using Verilog language, including the memory, controller,data path, the logic unit.
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File list (Check if you may need any files):
CPU\address logic.v
...\address logic.v.bak
...\condition decoder logic.v
...\condition decoder logic.v.bak
...\controller.v
...\controller.v.bak
...\cpu flags.v
...\cpu flags.v.bak
...\CPU.cr.mti
...\CPU.mpf
...\CPU.v
...\CPU.v.bak
...\datapath.v
...\datapath.v.bak
...\direction register.v
...\direction register.v.bak
...\hw89-report.docx
...\instruction register.v
...\instruction register.v.bak
...\logic unit.v
...\logic unit.v.bak
...\memory.v
...\memory.v.bak
...\program counter.v
...\program counter.v.bak
...\register file.v
...\register file.v.bak
...\tcl_stacktrace.txt
...\temporary register.v
...\temporary register.v.bak
...\test.v
...\test.v.bak
...\transcript
...\vsim.wlf
...\window pointer.v
...\window pointer.v.bak
...\.ork\@a@l\verilog.prw
...\....\....\verilog.psm
...\....\....\_primary.dat
...\....\....\_primary.dbs
...\....\....\_primary.vhd
...\....\....@u\verilog.prw
...\....\......\verilog.psm
...\....\......\_primary.dat
...\....\......\_primary.dbs
...\....\......\_primary.vhd
...\....\.c@d@l\verilog.prw
...\....\......\verilog.psm
...\....\......\_primary.dat
...\....\......\_primary.dbs
...\....\......\_primary.vhd
...\....\...z@n\verilog.prw
...\....\......\verilog.psm
...\....\......\_primary.dat
...\....\......\_primary.dbs
...\....\......\_primary.vhd
...\....\.d@i\verilog.prw
...\....\....\verilog.psm
...\....\....\_primary.dat
...\....\....\_primary.dbs
...\....\....\_primary.vhd
...\....\...p\verilog.prw
...\....\....\verilog.psm
...\....\....\_primary.dat
...\....\....\_primary.dbs
...\....\....\_primary.vhd
...\....\.i@r\verilog.prw
...\....\....\verilog.psm
...\....\....\_primary.dat
...\....\....\_primary.dbs
...\....\....\_primary.vhd
...\....\.m\verilog.prw
...\....\..\verilog.psm
...\....\..\_primary.dat
...\....\..\_primary.dbs
...\....\..\_primary.vhd
...\....\.p@c\verilog.prw
...\....\....\verilog.psm
...\....\....\_primary.dat
...\....\....\_primary.dbs
...\....\....\_primary.vhd
...\....\.r@f\verilog.prw
...\....\....\verilog.psm
...\....\....\_primary.dat
...\....\....\_primary.dbs
...\....\....\_primary.vhd
...\....\.t@r\verilog.prw
...\....\....\verilog.psm
...\....\....\_primary.dat
...\....\....\_primary.dbs
...\....\....\_primary.vhd
...\....\.w@p\verilog.prw
...\....\....\verilog.psm
...\....\....\_primary.dat
...\....\....\_primary.dbs
...\....\....\_primary.vhd
...\....\controller\verilog.prw
...\....\..........\verilog.psm
...\....\..........\_primary.dat
...\....\..........\_primary.dbs
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