Xilinx公司PCI Express IP核应用参考设计\ml505_pcie_x1_plus_compiled\ml505_pcie_x1_plus.cgp
......................................\...........................\pcie_blk_plus_v1_2\example_design\EP_MEM.v
......................................\...........................\..................\..............\pci_exp_1_lane_64b_ep.v
......................................\...........................\..................\..............\pci_exp_64b_app.v
......................................\...........................\..................\..............\PIO.v
......................................\...........................\..................\..............\PIO_64.v
......................................\...........................\..................\..............\PIO_64_RX_ENGINE.v
......................................\...........................\..................\..............\PIO_64_TX_ENGINE.v
......................................\...........................\..................\..............\PIO_EP.v
......................................\...........................\..................\..............\PIO_EP_MEM_ACCESS.v
......................................\...........................\..................\..............\PIO_TO_CTRL.v
......................................\...........................\..................\..............\xilinx_pci_exp_1_lane_ep.v
......................................\...........................\..................\..............\xilinx_pci_exp_1_lane_ep_product.v
......................................\...........................\..................\..............\xilinx_pci_exp_blk_plus_1_lane_ep-XC5VLX50T-FF1136-1.ucf
......................................\...........................\..................\..............\xilinx_pci_exp_blk_plus_1_lane_ep-XC5VLX50T-FF1136-1_ES.ucf
......................................\...........................\..................\implement\implement.bat
......................................\...........................\..................\.........\implement.log
......................................\...........................\..................\.........\implement.sh
......................................\...........................\..................\.........\make_ace.bat
......................................\...........................\..................\.........\pcie_ace.cmd
......................................\...........................\..................\.........\pcie_blk_plus_v1_1_top.ace
......................................\...........................\..................\.........\results\routed.bit
......................................\...........................\..................\.........\.......\routed.ncd
......................................\...........................\..................\.........\.......\routed.pad
......................................\...........................\..................\.........\.......\routed.par
......................................\...........................\..................\pcie_blk_plus_release_notes.txt
......................................\...........................\pcie_blk_plus_v1_2.ngc
......................................\...........................\pcie_blk_plus_v1_2.v
......................................\...........................\pcie_blk_plus_v1_2.veo
......................................\...........................\pcie_blk_plus_v1_2.xco
......................................\...........................\pcie_blk_plus_v1_2_flist.txt
......................................\...........................\pcie_blk_plus_v1_2_pcie_blk_plus_gen_1_vhdl.prj
......................................\...........................\pcie_blk_plus_v1_2_xmdf.tcl
......................................\pcie_blk_plus_v1_2\example_design\xilinx_pci_exp_blk_plus_1_lane_ep-XC5VLX50T-FF1136-1.ucf
......................................\..................\..............\xilinx_pci_exp_blk_plus_1_lane_ep-XC5VLX50T-FF1136-1_ES.ucf
......................................\..................\implement\implement.bat
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