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VHDL-FPGA-Verilog
Title:
crc_eth
Download
Category:
Algorithm
Tags:
[VHDL]
[源码]
File Size:
2kb
Update:
2012-11-26
Downloads:
0 Times
Uploaded by:
kkkadr
Description:
Verilog code to add a CRC field at the end of an ethernet frame.
Downloaders recently:
[
More information of uploader kkkadr
]
To Search:
ethernet crc
ethernet verilog
[
eathnet
] - Fast Ethernet MII and the VHDL source wa
[
parallel_CRC
] - Parallel Implementation of CRC checksum,
[
ethernet_tri_mode.rel-1-0.tar
] - ethernet mac verilog code.eth 10 100 100
[
crc
] - For implementing the CRC in verilog or V
File list
(Check if you may need any files):
crc32_d8_rev_for_tag.v crc_calculator.v
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