Description: serial port driver on the fpga, including the receiving host to the data (deserial) and send the data generated by the FPGA (serial) to pc. The program needs the serial debug debugging assistant
- [uart_verilog] - Simplified serial communication, removin
- [iic] - IIC bus standard Verilog source code i2c
- [D_AGC2] - FPGA digital AGC (help students to do th
- [Serial] - FPGA and the PC serial communication pro
- [serial_uart_top_new] - Series FPGA Cycloneii to test the serial
- [rs232] - fpga serial read and write procedures, b
- [FPGA-URAT] - FPGA and the PC serial port automaticall
- [FPGA_RS_232] - FPGA_RS_232
- [RS232(verilog)] - RS232 serial communication program, incl
File list (Check if you may need any files):
serial_com\async_receiver.v
..........\async_receiver_summary.html
..........\async_transmitter.v
..........\device_usage_statistics.html
..........\netgen\par\serialfun_timesim.nlf
..........\......\...\serialfun_timesim.sdf
..........\......\...\serialfun_timesim.v
..........\serialfun.bgn
..........\serialfun.bit
..........\serialfun.bld
..........\serialfun.cel
..........\serialfun.cmd_log
..........\serialfun.drc
..........\serialfun.lfp
..........\serialfun.lso
..........\serialfun.ncd
..........\serialfun.ngc
..........\serialfun.ngd
..........\serialfun.ngr
..........\serialfun.pad
..........\serialfun.par
..........\serialfun.pcf
..........\serialfun.prj
..........\serialfun.stx
..........\serialfun.syr
..........\serialfun.twr
..........\serialfun.twx
..........\serialfun.ucf
..........\serialfun.unroutes
..........\serialfun.ut
..........\serialfun.v
..........\serialfun.xpi
..........\serialfun.xst
..........\serialfun_guide.ncd
..........\serialfun_map.map
..........\serialfun_map.mrp
..........\serialfun_map.ncd
..........\serialfun_map.ngm
..........\serialfun_pad.csv
..........\serialfun_pad.txt
..........\serialfun_prev_built.ngd
..........\serialfun_summary.html
..........\serialfun_summary.xml
..........\serialfun_usage.xml
..........\serial_com.ise
..........\serial_com.ise_ISE_Backup
..........\serial_com.ntrc_log
..........\serial_com.restore
..........\serial_test.ant
..........\serial_test.jhd
..........\serial_test.tbw
..........\serial_test.tdo
..........\serial_test.tfw
..........\serial_test.udo
..........\serial_test.xwv
..........\serial_test.xwv_bak
..........\serial_test_bencher.prj
..........\transcript
..........\vsim.wlf
..........\work\glbl\verilog.psm
..........\....\....\_primary.dat
..........\....\....\_primary.vhd
..........\....\serialfun\verilog.psm
..........\....\.........\_primary.dat
..........\....\.........\_primary.vhd
..........\....\......_test\verilog.psm
..........\....\...........\_primary.dat
..........\....\...........\_primary.vhd
..........\....\_info
..........\xst\dump.xst\serialfun.prj\ntrc.scr
..........\...\work\hdllib.ref
..........\...\....\vlg32\async__transmitter.bin
..........\...\....\....A\async__receiver.bin
..........\...\....\...4D\serialfun.bin
..........\_ngo\netlist.lst
..........\_pace.ucf
..........\.xmsgs\bitgen.xmsgs
..........\......\map.xmsgs
..........\......\netgen.xmsgs
..........\......\ngdbuild.xmsgs
..........\......\par.xmsgs
..........\......\trce.xmsgs
..........\......\xst.xmsgs
..........\xst\dump.xst\serialfun.prj\ngx\notopt
..........\...\........\.............\...\opt
..........\...\........\.............\ngx
..........\...\........\serialfun.prj
..........\...\work\vlg32
..........\...\....\vlg3A
..........\...\....\vlg4D
..........\netgen\par
..........\work\glbl
..........\....\serialfun
..........\....\serial_test
..........\....\_temp
..........\xst\dump.xst
..........\...\projnav.tmp
..........\...\work
..........\netgen
..........\work
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