Description: VHDL language design with a RISC processor with 10 instruction. Assume that main memory can be completed in one cycle is always followed and the CPU read and write operations and the synchronization system uses a main memory unit. 16-bit instruction word processor, including 8 general purpose registers, a 16-bit instruction register and a 16-bit program counter. Processor' s address bus width 16 bits. 16-bit data bus width, fetch and data access are in the hop hoppers data bus. Processor support includes LDA, STA, MOV, MVI, ADD, SUB, AND, OR, JZ, JMP ten instructions. LDA and STA is the only one memory access instructions.
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File list (Check if you may need any files):
zxcpu\.untf
.....\automake.log
.....\back.ANT
.....\back.fdo
.....\back.tbw
.....\back.udo
.....\back.vhw
.....\backwr.cmd_log
.....\backwr.lso
.....\backwr.ngc
.....\backwr.ngr
.....\backwr.prj
.....\backwr.stx
.....\backwr.syr
.....\backwr.vhdl
.....\bitgen.ut
.....\clk.ANT
.....\clk.fdo
.....\clk.tbw
.....\clk.udo
.....\clk.vhw
.....\clock.cmd_log
.....\clock.lso
.....\clock.ngc
.....\clock.ngr
.....\clock.prj
.....\clock.stx
.....\clock.syr
.....\clock.vhdl
.....\coregen.log
.....\coregen.prj
.....\coregen_lock
.....\CPU
.....\cpu.bgn
.....\cpu.bit
.....\cpu.bld
.....\cpu.cmd_log
.....\cpu.dhp
.....\cpu.drc
.....\cpu.lso
.....\cpu.mrp
.....\cpu.nc1
.....\cpu.ncd
.....\cpu.ngc
.....\cpu.ngd
.....\cpu.ngm
.....\cpu.ngr
.....\cpu.npl
.....\cpu.pad
.....\cpu.pad_txt
.....\cpu.par
.....\cpu.pcf
.....\cpu.placed_ncd_tracker
.....\cpu.prj
.....\cpu.routed_ncd_tracker
.....\cpu.stx
.....\cpu.syr
.....\cpu.twr
.....\cpu.twx
.....\cpu.ucf
.....\cpu.ucf.untf
.....\cpu.ut
.....\cpu.vhdl
.....\cpu.xpi
.....\cpuall.vhdl
.....\CPUdata
.....\cpuw.ANT
.....\cpuw.fdo
.....\cpuw.tbw
.....\cpuw.udo
.....\cpuw.vhw
.....\cpu_last_par.ncd
.....\cpu_map.ncd
.....\cpu_map.ngm
.....\cpu_pad.csv
.....\cpu_pad.txt
.....\fet.ANT
.....\fet.fdo
.....\fet.tbw
.....\fet.udo
.....\fet.vhw
.....\fetch.cmd_log
.....\fetch.lso
.....\fetch.ngc
.....\fetch.ngr
.....\fetch.prj
.....\fetch.stx
.....\fetch.syr
.....\fetch.vhdl
.....\mem.ANT
.....\mem.fdo
.....\mem.tbw
.....\mem.udo
.....\mem.vhw
.....\memory.cmd_log
.....\memory.lso
.....\memory.ngc
.....\memory.ngr
.....\memory.prj
.....\memory.stx
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