Description: 16 bit CPU design, adopt VHDL language, bring test assembly language, can realize basic operation and shift, jump and so on operation -16-bit CPU design, using VHDL language, self-test assembly language, to achieve the basic operations and shift operations such as jump
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CPU\8CPU.asm.rpt
...\8CPU.done
...\8CPU.dpf
...\8CPU.fit.rpt
...\8CPU.fit.summary
...\8CPU.flow.rpt
...\8CPU.map.rpt
...\8CPU.map.summary
...\8CPU.pin
...\8CPU.pof
...\8CPU.qpf
...\8CPU.qsf
...\8CPU.sof
...\8CPU.tan.rpt
...\8CPU.tan.summary
...\ALU.bsf
...\ALU.vhd
...\aluuu.bdf
...\Block1.bdf
...\CPU.vhd
...\CPU.vhd.bak
...\cpu_defs.vhd
...\CU.vhd
...\CU.vhd.bak
...\db\8CPU.asm.qmsg
...\..\8CPU.cbx.xml
...\..\8CPU.cmp.cdb
...\..\8CPU.cmp.hdb
...\..\8CPU.cmp.logdb
...\..\8CPU.cmp.rdb
...\..\8CPU.cmp.tdb
...\..\8CPU.cmp0.ddb
...\..\8CPU.db_info
...\..\8CPU.eco.cdb
...\..\8CPU.fit.qmsg
...\..\8CPU.hier_info
...\..\8CPU.hif
...\..\8CPU.lpc.html
...\..\8CPU.lpc.rdb
...\..\8CPU.lpc.txt
...\..\8CPU.map.cdb
...\..\8CPU.map.hdb
...\..\8CPU.map.logdb
...\..\8CPU.map.qmsg
...\..\8CPU.pre_map.cdb
...\..\8CPU.pre_map.hdb
...\..\8CPU.rtlv.hdb
...\..\8CPU.rtlv_sg.cdb
...\..\8CPU.rtlv_sg_swap.cdb
...\..\8CPU.sgdiff.cdb
...\..\8CPU.sgdiff.hdb
...\..\8CPU.sld_design_entry.sci
...\..\8CPU.sld_design_entry_dsc.sci
...\..\8CPU.smp_dump.txt
...\..\8CPU.syn_hier_info
...\..\8CPU.tan.qmsg
...\..\8CPU.tis_db_list.ddb
...\..\8CPU.tmw_info
...\..\add_sub_4lh.tdf
...\..\add_sub_fnh.tdf
...\..\add_sub_lch.tdf
...\..\add_sub_sjh.tdf
...\..\prev_cmp_8CPU.asm.qmsg
...\..\prev_cmp_8CPU.fit.qmsg
...\..\prev_cmp_8CPU.map.qmsg
...\..\prev_cmp_8CPU.qmsg
...\..\prev_cmp_8CPU.tan.qmsg
...\incremental_db\compiled_partitions\8CPU.root_partition.map.kpt
...\..............\README
...\IR.bsf
...\IR.vhd
...\PC.vhd
...\RAM.vhd
...\reg.vhd
...\reg.vhd.bak
...\registers.vhd
...\ROM.vhd
...\ROM.vhd.bak
...\shift.vhd
...\trireg.vhd
...\incremental_db\compiled_partitions
...\db
...\incremental_db
CPU
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