risc
....\accum.v
....\addr_decode.v
....\adr.v
....\alu.v
....\clk_gen.v
....\counter.v
....\cpu.v
....\datactl.v
....\machine.v
....\machinectl.v
....\ram.v
....\register.v
....\RISC_CPU - FPGA.doc
....\test1.dat
....\test1.pro