Description: This design is based on the large-scale FPGA-BMP library management, and completed part of the features of digital photo frame. This paper describes the library management software and hardware to achieve BMP photos, that used the Altera s CyclonII series EP2C20F484C7 as the master chip, embedded soft-core 32-bit NiosII, the use of SDRAM for memory, SD card stored the binary picture information read into memory, and control TFT color LCD, read the image form the memory data to the LCD display. All equipment of the process hanging in the NiosII through Avalon bus, with the NiosII CPU and complete the coordination of work.
Eventually the work can show the color pictures of information stored into the SD card, pictures show smoothly, and with no delay. And with 4 keys, respectively, we can make the TFT display the previous image or the next image,and make the pictures zoom in or zoom out.
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File list (Check if you may need any files):
DE1_fat32\.sopc_builder\filters.xml
.........\.............\install.ptf
.........\.............\install2.ptf
.........\.............\preferences.xml
.........\320240A.JPG
.........\altpll0.bsf
.........\altpll0.cmp
.........\altpll0.ppf
.........\altpll0.qip
.........\altpll0.vhd
.........\altpll0_wave0.jpg
.........\altpll0_waveforms.html
.........\clk_spi.vhd
.........\cpu_0.ocp
.........\cpu_0.sdc
.........\cpu_0.vhd
.........\cpu_0_bht_ram.mif
.........\cpu_0_dc_tag_ram.mif
.........\cpu_0_ic_tag_ram.mif
.........\cpu_0_jtag_debug_module_sysclk.vhd
.........\cpu_0_jtag_debug_module_tck.vhd
.........\cpu_0_jtag_debug_module_wrapper.vhd
.........\cpu_0_mult_cell.vhd
.........\cpu_0_ociram_default_contents.mif
.........\cpu_0_oci_test_bench.vhd
.........\cpu_0_rf_ram.mif
.........\cpu_0_rf_ram_a.mif
.........\cpu_0_rf_ram_b.mif
.........\cpu_0_test_bench.vhd
.........\cs_spi.vhd
.........\db\altsyncram_0ff1.tdf
.........\..\altsyncram_1l22.tdf
.........\..\altsyncram_29f1.tdf
.........\..\altsyncram_2ef1.tdf
.........\..\altsyncram_4ef1.tdf
.........\..\altsyncram_4hf1.tdf
.........\..\altsyncram_5bg1.tdf
.........\..\altsyncram_87f1.tdf
.........\..\altsyncram_8hf1.tdf
.........\..\altsyncram_8pf1.tdf
.........\..\altsyncram_97f1.tdf
.........\..\altsyncram_9o83.tdf
.........\..\altsyncram_9tl1.tdf
.........\..\altsyncram_9vc1.tdf
.........\..\altsyncram_afd1.tdf
.........\..\altsyncram_amf1.tdf
.........\..\altsyncram_c572.tdf
.........\..\altsyncram_d5g1.tdf
.........\..\altsyncram_e502.tdf
.........\..\altsyncram_f5g1.tdf
.........\..\altsyncram_gef1.tdf
.........\..\altsyncram_gff1.tdf
.........\..\altsyncram_h5g1.tdf
.........\..\altsyncram_i5g1.tdf
.........\..\altsyncram_irf1.tdf
.........\..\altsyncram_jrf1.tdf
.........\..\altsyncram_qed1.tdf
.........\..\altsyncram_qfd1.tdf
.........\..\altsyncram_v631.tdf
.........\..\a_dpfifo_8t21.tdf
.........\..\a_fefifo_7cf.tdf
.........\..\cntr_fjb.tdf
.........\..\cntr_rj7.tdf
.........\..\decode_1oa.tdf
.........\..\ded_mult_2o81.tdf
.........\..\dffpipe_93c.tdf
.........\..\dpram_5h21.tdf
.........\..\mult_add_4cr2.tdf
.........\..\mult_add_6cr2.tdf
.........\..\mux_2kb.tdf
.........\..\mux_ujb.tdf
.........\..\NIOS_TFT.asm.qmsg
.........\..\NIOS_TFT.asm_labs.ddb
.........\..\NIOS_TFT.cbx.xml
.........\..\NIOS_TFT.cmp.bpm
.........\..\NIOS_TFT.cmp.cdb
.........\..\NIOS_TFT.cmp.ecobp
.........\..\NIOS_TFT.cmp.hdb
.........\..\NIOS_TFT.cmp.kpt
.........\..\NIOS_TFT.cmp.logdb
.........\..\NIOS_TFT.cmp.rdb
.........\..\NIOS_TFT.cmp.tdb
.........\..\NIOS_TFT.cmp0.ddb
.........\..\NIOS_TFT.cmp2.ddb
.........\..\NIOS_TFT.cmp_merge.kpt
.........\..\NIOS_TFT.db_info
.........\..\NIOS_TFT.eco.cdb
.........\..\NIOS_TFT.fit.qmsg
.........\..\NIOS_TFT.hier_info
.........\..\NIOS_TFT.hif
.........\..\NIOS_TFT.lpc.html
.........\..\NIOS_TFT.lpc.rdb
.........\..\NIOS_TFT.lpc.txt
.........\..\NIOS_TFT.map.bpm
.........\..\NIOS_TFT.map.cdb
.........\..\NIOS_TFT.map.ecobp
.........\..\NIOS_TFT.map.hdb
.........\..\NIOS_TFT.map.kpt
.........\..\NIOS_TFT.map.logdb
.........\..\NIOS_TFT.map.qmsg
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