Description: This procedure implemented based on FPGA/CPLD' s VGA display design, easy to understand, you can output 8 colors, the three RGB colors, a total of 8 combinations. FPGA to VGA port connector and LCD monitors and other experimental phenomena can be observed.
To Search:
File list (Check if you may need any files):
vgaverilog\db\prev_cmp_vga_dis.asm.qmsg
..........\..\prev_cmp_vga_dis.fit.qmsg
..........\..\prev_cmp_vga_dis.map.qmsg
..........\..\prev_cmp_vga_dis.qmsg
..........\..\prev_cmp_vga_dis.tan.qmsg
..........\..\vga_dis.asm.qmsg
..........\..\vga_dis.asm_labs.ddb
..........\..\vga_dis.cbx.xml
..........\..\vga_dis.cmp.cdb
..........\..\vga_dis.cmp.hdb
..........\..\vga_dis.cmp.kpt
..........\..\vga_dis.cmp.logdb
..........\..\vga_dis.cmp.rdb
..........\..\vga_dis.cmp.tdb
..........\..\vga_dis.cmp0.ddb
..........\..\vga_dis.cmp2.ddb
..........\..\vga_dis.db_info
..........\..\vga_dis.eco.cdb
..........\..\vga_dis.fit.qmsg
..........\..\vga_dis.hier_info
..........\..\vga_dis.hif
..........\..\vga_dis.lpc.html
..........\..\vga_dis.lpc.rdb
..........\..\vga_dis.lpc.txt
..........\..\vga_dis.map.cdb
..........\..\vga_dis.map.hdb
..........\..\vga_dis.map.logdb
..........\..\vga_dis.map.qmsg
..........\..\vga_dis.pre_map.cdb
..........\..\vga_dis.pre_map.hdb
..........\..\vga_dis.rtlv.hdb
..........\..\vga_dis.rtlv_sg.cdb
..........\..\vga_dis.rtlv_sg_swap.cdb
..........\..\vga_dis.sgdiff.cdb
..........\..\vga_dis.sgdiff.hdb
..........\..\vga_dis.sld_design_entry.sci
..........\..\vga_dis.sld_design_entry_dsc.sci
..........\..\vga_dis.syn_hier_info
..........\..\vga_dis.tan.qmsg
..........\..\vga_dis.tis_db_list.ddb
..........\..\vga_dis.tmw_info
..........\..\vga_dis_global_asgn_op.abo
..........\incremental_db\compiled_partitions\vga_dis.root_partition.map.kpt
..........\..............\README
..........\vga_dis.asm.rpt
..........\vga_dis.cdf
..........\vga_dis.done
..........\vga_dis.dpf
..........\vga_dis.fit.rpt
..........\vga_dis.fit.smsg
..........\vga_dis.fit.summary
..........\vga_dis.flow.rpt
..........\vga_dis.map.rpt
..........\vga_dis.map.summary
..........\vga_dis.pin
..........\vga_dis.pof
..........\vga_dis.qpf
..........\vga_dis.qsf
..........\vga_dis.qws
..........\vga_dis.sof
..........\vga_dis.tan.rpt
..........\vga_dis.tan.summary
..........\vga_dis.v
..........\vga_dis.v.bak
..........\vga_dis_assignment_defaults.qdf
..........\incremental_db\compiled_partitions
..........\db
..........\incremental_db
vgaverilog
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