用VHDL写的电子琴的小程序(整个工程文件)\piano\clk1mtolow.bmp
......................................\.....\clk64toclap.bmp
......................................\.....\counter.alr
......................................\.....\counter.ASX
......................................\.....\counter.bak
......................................\.....\counter.bmp
......................................\.....\counter.edf
......................................\.....\counter.ENT
......................................\.....\counter.ER
......................................\.....\counter.log
......................................\.....\counter.opt
......................................\.....\counter.vhd
......................................\.....\displayencoding.alr
......................................\.....\displayencoding.ASX
......................................\.....\displayencoding.bak
......................................\.....\displayencoding.bmp
......................................\.....\displayencoding.edf
......................................\.....\displayencoding.ENT
......................................\.....\displayencoding.ER
......................................\.....\displayencoding.log
......................................\.....\displayencoding.opt
......................................\.....\displayencoding.vhd
......................................\.....\DPMCOMP.TMP\chips\keysampling\keysampling.cst
......................................\.....\...........\.....\...........\keysampling.rpt
......................................\.....\...........\.....\...........\keysampling.ws
......................................\.....\...........\.....\..........._OPT\keysampling_OPT.cst
......................................\.....\...........\.....\...............\keysampling_OPT.rpt
......................................\.....\...........\.....\...............\keysampling_OPT.ws
......................................\.....\...........\DPMCOMP.TMP.exp
......................................\.....\...........\files\L0.rpt
......................................\.....\...........\workdirs\WORK\Anal.info
......................................\.....\...........\........\....\Anal.out
......................................\.....\...........\........\....\keysampling.hnl
......................................\.....\...........\........\....\KEYSAMPLING.mra
......................................\.....\...........\........\....\keysampling.out
......................................\.....\...........\........\....\KEYSAMPLING.sim
......................................\.....\...........\........\....\keysampling.sts
......................................\.....\...........\........\....\KEYSAMPLING.syn
......................................\.....\...........\........\....\KEYSAMPLING__KEYSAMPLING_ARCH.sim
......................................\.....\...........\........\....\KEYSAMPLING__KEYSAMPLING_ARCH.syn
......................................\.....\ErrLog.log
......................................\.....\exp_EDIF.log
......................................\.....\fenpin10mtolow.alr
......................................\.....\fenpin10mtolow.ASX
......................................\.....\fenpin10mtolow.bak
......................................\.....\fenpin10mtolow.edf
......................................\.....\fenpin10mtolow.ENT
......................................\.....\fenpin10mtolow.ER
......................................\.....\fenpin10mtolow.log
......................................\.....\fenpin10mtolow.opt
......................................\.....\fenpin10mtolow.vhd
......................................\.....\fenpin64toclap.alr
......................................\.....\fenpin64toclap.ASX
......................................\.....\fenpin64toclap.bak
......................................\.....\fenpin64toclap.edf
......................................\.....\fenpin64toclap.ENT
......................................\.....\fenpin64toclap.ER
......................................\.....\fenpin64toclap.log
.................