Description: An SRAM controller, included documentation. Set the address and input data, complete the write function, enter the address again to complete the reading function.
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File list (Check if you may need any files):
SRAMtest\db\SRAMtest.analyze_file.qmsg
........\..\SRAMtest.asm.qmsg
........\..\SRAMtest.asm_labs.ddb
........\..\SRAMtest.cbx.xml
........\..\SRAMtest.cmp.bpm
........\..\SRAMtest.cmp.cdb
........\..\SRAMtest.cmp.ecobp
........\..\SRAMtest.cmp.hdb
........\..\SRAMtest.cmp.logdb
........\..\SRAMtest.cmp.rdb
........\..\SRAMtest.cmp.tdb
........\..\SRAMtest.cmp0.ddb
........\..\SRAMtest.cmp_bb.cdb
........\..\SRAMtest.cmp_bb.hdb
........\..\SRAMtest.cmp_bb.logdb
........\..\SRAMtest.cmp_bb.rcf
........\..\SRAMtest.dbp
........\..\SRAMtest.db_info
........\..\SRAMtest.eco.cdb
........\..\SRAMtest.eds_overflow
........\..\SRAMtest.fit.qmsg
........\..\SRAMtest.fnsim.hdb
........\..\SRAMtest.fnsim.qmsg
........\..\SRAMtest.hier_info
........\..\SRAMtest.hif
........\..\SRAMtest.map.bpm
........\..\SRAMtest.map.cdb
........\..\SRAMtest.map.ecobp
........\..\SRAMtest.map.hdb
........\..\SRAMtest.map.logdb
........\..\SRAMtest.map.qmsg
........\..\SRAMtest.map_bb.cdb
........\..\SRAMtest.map_bb.hdb
........\..\SRAMtest.map_bb.logdb
........\..\SRAMtest.merge.qmsg
........\..\SRAMtest.pre_map.cdb
........\..\SRAMtest.pre_map.hdb
........\..\SRAMtest.psp
........\..\SRAMtest.pss
........\..\SRAMtest.rtlv.hdb
........\..\SRAMtest.rtlv_sg.cdb
........\..\SRAMtest.rtlv_sg_swap.cdb
........\..\SRAMtest.sgdiff.cdb
........\..\SRAMtest.sgdiff.hdb
........\..\SRAMtest.signalprobe.cdb
........\..\SRAMtest.sim.cvwf
........\..\SRAMtest.sim.hdb
........\..\SRAMtest.sim.qmsg
........\..\SRAMtest.sim.rdb
........\..\SRAMtest.sld_design_entry.sci
........\..\SRAMtest.sld_design_entry_dsc.sci
........\..\SRAMtest.smp_dump.txt
........\..\SRAMtest.syn_hier_info
........\..\SRAMtest.tan.qmsg
........\..\wed.wsf
........\Reset_Delay.v
........\SEG7_LUT.v
........\SEG7_LUT_4.v
........\SEG7_LUT_4.v.bak
........\SRAMtest.asm.rpt
........\SRAMtest.cdf
........\SRAMtest.cr.mti
........\SRAMtest.done
........\SRAMtest.fit.rpt
........\SRAMtest.fit.smsg
........\SRAMtest.fit.summary
........\SRAMtest.flow.rpt
........\SRAMtest.map.rpt
........\SRAMtest.map.smsg
........\SRAMtest.map.summary
........\SRAMtest.merge.rpt
........\SRAMtest.mpf
........\SRAMtest.pin
........\SRAMtest.pof
........\SRAMtest.qpf
........\SRAMtest.qsf
........\SRAMtest.qsf.bak
........\SRAMtest.qws
........\SRAMtest.sim.rpt
........\SRAMtest.sof
........\SRAMtest.tan.rpt
........\SRAMtest.tan.summary
........\SRAMtest.v
........\SRAMtest.v.bak
........\SRAMtest.vwf
........\SRAM_16Bit_512K.v
........\SRAM_16Bit_512K.xml
........\SRAM_16Bit_512K_tb.v
........\SRAM_16Bit_512K_tb.v.bak
........\transcript
........\vsim.wlf
........\Waveform1.vwf
........\work\@reset_@delay\verilog.asm
........\....\.............\_primary.dat
........\....\.............\_primary.vhd
........\....\.s@e@g7_@l@u@t\verilog.asm
........\....\..............\_primary.dat
........\....\..............\_primary.vhd
........\....\.............._4\verilog.asm
........\....\................\_primary.dat
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