spi
...\branches
__MACOSX
........\spi
........\...\._branches
spi\tags
...\....\asyst_2
...\....\.......\rtl
...\....\.......\...\verilog
...\....\.......\...\.......\spi_clgen.v
...\....\.......\...\.......\spi_defines.v
__MACOSX\spi\tags
........\...\....\asyst_2
........\...\....\.......\rtl
........\...\....\.......\...\verilog
........\...\....\.......\...\.......\._spi_defines.v
spi\tags\asyst_2\rtl\verilog\spi_shift.v
...\....\.......\...\.......\spi_top.v
__MACOSX\spi\tags\asyst_2\rtl\verilog\._spi_top.v
spi\tags\asyst_2\rtl\verilog\timescale.v
__MACOSX\spi\tags\asyst_2\rtl\verilog\._timescale.v
........\...\....\.......\...\._verilog
........\...\....\.......\._rtl
........\...\....\._asyst_2
spi\tags\asyst_3
...\....\.......\rtl
...\....\.......\...\verilog
...\....\.......\...\.......\spi_clgen.v
__MACOSX\spi\tags\asyst_3
........\...\....\.......\rtl
........\...\....\.......\...\verilog
........\...\....\.......\...\.......\._spi_clgen.v
spi\tags\asyst_3\rtl\verilog\spi_defines.v
__MACOSX\spi\tags\asyst_3\rtl\verilog\._spi_defines.v
spi\tags\asyst_3\rtl\verilog\spi_shift.v
...\....\.......\...\.......\spi_top.v
__MACOSX\spi\tags\asyst_3\rtl\verilog\._spi_top.v
spi\tags\asyst_3\rtl\verilog\timescale.v
__MACOSX\spi\tags\asyst_3\rtl\verilog\._timescale.v
........\...\....\.......\...\._verilog
........\...\....\.......\._rtl
........\...\....\._asyst_3
spi\tags\initial
...\....\.......\bench
...\....\.......\.....\verilog
...\....\.......\.....\.......\spi_slave_model.v
...\....\.......\.....\.......\tb_spi_top.v
...\....\.......\.....\.......\wb_master_model.v
__MACOSX\spi\tags\initial
........\...\....\.......\bench
........\...\....\.......\.....\._verilog
........\...\....\.......\._bench
spi\tags\initial\doc
...\....\.......\...\src
...\....\.......\...\...\spi.doc
__MACOSX\spi\tags\initial\doc
........\...\....\.......\...\src
........\...\....\.......\...\...\._spi.doc
........\...\....\.......\...\._src
........\...\....\.......\._doc
spi\tags\initial\rtl
...\....\.......\...\verilog
...\....\.......\...\.......\spi_clgen.v
__MACOSX\spi\tags\initial\rtl
........\...\....\.......\...\verilog
........\...\....\.......\...\.......\._spi_clgen.v
spi\tags\initial\rtl\verilog\spi_defines.v
__MACOSX\spi\tags\initial\rtl\verilog\._spi_defines.v
spi\tags\initial\rtl\verilog\spi_shift.v
__MACOSX\spi\tags\initial\rtl\verilog\._spi_shift.v
spi\tags\initial\rtl\verilog\spi_top.v
__MACOSX\spi\tags\initial\rtl\verilog\._spi_top.v
spi\tags\initial\rtl\verilog\timescale.v
__MACOSX\spi\tags\initial\rtl\verilog\._timescale.v
........\...\....\.......\...\._verilog
........\...\....\.......\._rtl
spi\tags\initial\sim
...\....\.......\...\run
...\....\.......\...\...\sim
__MACOSX\spi\tags\initial\sim
........\...\....\.......\...\run
........\...\....\.......\...\...\._sim
spi\tags\initial\sim\run\tcl.scr
__MACOSX\spi\tags\initial\sim\run\._tcl.scr
........\...\....\.......\...\._run
........\...\....\.......\._sim
........\...\....\._initial
spi\tags\rel_1
...\....\.....\bench
...\....\.....\.....\verilog
...\....\.....\.....\.......\spi_slave_model.v
__MACOSX\spi\tags\rel_1
........\...\....\.....\bench
........\...\....\.....\.....\verilog
........\...\....\.....\.....\.......\._spi_slave_model.v
spi\tags\rel_1\bench\verilog\tb_spi_top.v
__MACOSX\spi\tags\rel_1\bench\verilog\._tb_spi_top.v
spi\tags\rel_1\bench\verilog\wb_master_model.v
__MACOSX\spi\tags\rel_1\bench\verilog\._wb_master_model.v
........\...\....\.....\.....\._verilog