Chipscope_Slides_labs\Chipscope_pro_lab
.....................\.................\training
.....................\.................\........\chipscope_pro
.....................\.................\........\.............\completed
.....................\.................\........\.............\.........\CoreGenFlow-Verilog
.....................\.................\........\.............\.........\...................\CoreGenFlow.gise
.....................\.................\........\.............\.........\...................\CoreGenFlow.xise
.....................\.................\........\.............\.........\...................\examplecoregen.bgn
.....................\.................\........\.............\.........\...................\examplecoregen.bit
.....................\.................\........\.............\.........\...................\exampleCoreGen.bld
.....................\.................\........\.............\.........\...................\exampleCoreGen.cmd_log
.....................\.................\........\.............\.........\...................\exampleCoreGen.cpj
.....................\.................\........\.............\.........\...................\examplecoregen.drc
.....................\.................\........\.............\.........\...................\exampleCoreGen.lso
.....................\.................\........\.............\.........\...................\exampleCoreGen.ncd
.....................\.................\........\.............\.........\...................\exampleCoreGen.ngc
.....................\.................\........\.............\.........\...................\exampleCoreGen.ngd
.....................\.................\........\.............\.........\...................\exampleCoreGen.ngr
.....................\.................\........\.............\.........\...................\exampleCoreGen.pad
.....................\.................\........\.............\.........\...................\exampleCoreGen.par
.....................\.................\........\.............\.........\...................\exampleCoreGen.pcf
.....................\.................\........\.............\.........\...................\exampleCoreGen.prj
.....................\.................\........\.............\.........\...................\exampleCoreGen.ptwx
.....................\.................\........\.............\.........\...................\exampleCoreGen.stx
.....................\.................\........\.............\.........\...................\exampleCoreGen.syr
.....................\.................\........\.............\.........\...................\exampleCoreGen.twr
.....................\.................\........\.............\.........\...................\exampleCoreGen.twx
.....................\.................\........\.............\.........\...................\exampleCoreGen.unroutes
.....................\.................\........\.............\.........\...................\exampleCoreGen.ut
.....................\.................\........\.............\.........\...................\exampleCoreGen.v
.....................\.................\........\.............\.........\...................\exampleCoreGen.xpi
.....................\.................\........\.............\.........\...................\exampleCoreGen.xst
.....................\.................\........\.............\.........\...................\exampleCoreGen_bitgen.xwbt
.....................\.................\........\.............\.........\...................\exampleCoreGen_envsettings.html
.....................\.................\........\.............\.........\...................\exampleCoreGen_guide.ncd
.....................\.................\........\.............\.........\...................\exampleCoreGen_map.map
.....................\.................\........\.............\.........\...................\exampleCoreGen_map.mrp
.....................\.................\........\.............\.........\...................\exampleCoreGen_map.ncd
.....................\.................\