clock-a-stopwatch DE2-70-based platform, enabling - CodeBus

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VHDL-FPGA-Verilog

Title: clock-a-stopwatch

Category:
VHDL-FPGA-Verilog
Tags:
[C/C++] [源码]
File Size:
2kb
Update:
2012-11-26
Downloads:
0 Times
Uploaded by:
Robert_zts

Description: DE2-70-based platform, enabling functions: 1、display time on the LCD 2、display stopwatch the digital tube

Downloaders recently: [More information of uploader Robert_zts]

To Search:

[ram_verilog] - This programe describe the properties of
[FPGA-and-DS18B20] - FPGA chip with the DS18B20 temperature a

File list (Check if you may need any files):

实验四\clock.c
......\clock.h
实验四

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