Description: Data recovery allows a receiver to extract embedded clock data from an incoming data stream.
The receiver usually extracts the data from the incoming clock/data stream and then moves this
data into a separate clock domain. Sometimes, the receiver’s clock is also used for onward data
transmission. The circuit described in this application note provides a partial solution at data
rates up to 160 Mb/s in a Virtex™ -E -7 device and a Spartan™ -IIE -6 device, up to 320 Mb/s for
a Spartan-3 -4 device, and up to 420Mb/s in a Virtex-II -5 device or a Virtex-II Pro -6 device.
The solution is partial in the sense that no clock is actually recovered, but the data arriving is
fully extracted. The speed is limited by the maximum frequency that can be accepted by the
Data Locked Loop (DLL), in a mode where the DLL is capable of providing both a new clock,
and another clock shifted by 90 degrees.
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File list (Check if you may need any files):
xapp224——datarecovery\xapp224\basic\virtex2\verilog\design_files\data_recovery_virtex2.v
.......................\.......\.....\.......\.......\............\data_recovery_virtex2_fast.v
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.......................\.......\.....\.......\.......\..........\top_v2.do
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.......................\.......\.....\.......\.......\ucf\TOP_V2.UCF
.......................\.......\.....\.......\.......\...\top_v2_fast.ucf
.......................\.......\.....\.......\.hdl\design_files\data_recovery_virtex2.vhd
.......................\.......\.....\.......\....\............\data_recovery_virtex2_fast.vhd
.......................\.......\.....\.......\....\............\top_v2.vhd
.......................\.......\.....\.......\....\............\top_v2_fast.vhd
.......................\.......\.....\.......\....\simulation\tb_top_v2.VHD
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.......................\.......\.....\.......\....\..........\top_v2.do
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.......................\.......\.....\.......\....\ucf\TOP_V2.UCF
.......................\.......\.....\.......\....\...\top_v2_fast.ucf
.......................\.......\.....\......E\verilog\design_files\data_recovery_virtexe.v
.......................\.......\.....\.......\.......\............\top_ve.v
.......................\.......\.....\.......\.......\simulation\tb_top_ve.v
.......................\.......\.....\.......\.......\..........\tb_top_ve.vhd
.......................\.......\.....\.......\.......\..........\top_ve.do
.......................\.......\.....\.......\.......\ucf\TOP_VE.UCF
.......................\.......\.....\.......\.hdl\design_files\data_recovery_virtexe.vhd
.......................\.......\.....\.......\....\............\top_ve.vhd
.......................\.......\.....\.......\....\simulation\tb_top_ve.vhd
.......................\.......\.....\.......\....\..........\top_ve.do
.......................\.......\.....\.......\....\ucf\TOP_VE.UCF
.......................\.......\demo_board\virtex2\vhdl\design_files\data_recovery_virtex2.vhd
.......................\.......\..........\.......\....\............\data_recovery_virtex2_fast.vhd
.......................\.......\..........\.......\....\............\pn23.vhd
.......................\.......\..........\.......\....\............\top.vhd
.......................\.......\..........\.......\....\............\top_fast.vhd
.......................\.......\..........\.......\....\simulation\tb_top.VHD
.......................\.......\..........\.......\....\..........\tb_top_fast.VHD
.......................\.......\..........\.......\....\..........\top.do
.......................\.......\..........\.......\....\..........\top_fast.do
.......................\.......\..........\.......\....\ucf\top.UCF
.......................\.......\..........\.......\....\...\top_fast.ucf
.......................\.......\README.txt
.......................\.......\basic\virtex2\verilog\design_files
.......................\.......\.....\.......\.......\simulation
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.......................\.......\.....\......E\verilog\design_files
.......................\.......\.....\.......\.......\simulation
.......................\.......\.....\.......\.......\ucf
.......................\.......\.....\.......\.hdl\design_files
.......................\.......\.....\.......\....\simulation
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