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Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: a Download
 Description: mips single cycle verilog code for add,sub,bne,slt,lw,sw,xori instructions
 Downloaders recently: [More information of uploader nhanelectronic]
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File list (Check if you may need any files): 
a\data.dat
.\instr.dat
.\MIPS2.v
.\mipstim.v
a

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